dut Entity Reference

Design Under Test. More...

Inheritance diagram for dut:

List of all members.

Entities
RTL	architecture
Ports
data_out	out std_logic_vector ( 7 downto 0 )
	data out port comment
data_in	in std_logic_vector ( 7 downto 0 )
	data in port comment
valid	out std_logic
start	in std_logic
clock	in std_logic
reset	in std_logic

---

Detailed Description

Design Under Test.

---

Member Data Documentation

data_out out std_logic_vector ( 7 downto 0 ) [Port]

data out port comment

data_in in std_logic_vector ( 7 downto 0 ) [Port]

data in port comment

valid out std_logic [Port]

start in std_logic [Port]

clock in std_logic [Port]

reset in std_logic [Port]

---

The documentation for this class was generated from the following file:

• dut.vhd