Already for a long time, SystemVerilog UVM projects can be easily set up in Sigasi Studio. When you’re using our extension for VS Code, the setup can be even faster. In this article, I’ll show a few simple steps to configure a UVM example project.
I’m using the UVM 1.2 Reference Implementation since it comes with examples that make it easy to demonstrate the UVM project setup.
The following steps will lead to the setup of the ubus
example UVM project.
-
After downloading and extracting the UVM reference implementation, open the folder
uvm-1.2/examples/integrated/ubus
in a new VS Code window. -
If there is no Sigasi project yet, create one by opening the Command Palette using Ctrl+Shift+P and typing the command Sigasi: Add (System)Verilog Support. After doing so, you should see the Sigasi extension activating and the Problems View being populated.
-
The Sigasi extension provides a new Project View which you should open now. To open this view, navigate to the Explorer pane (Ctrl+Shift+E) and open the PROJECT VIEW element. This view replaces the default VS Code Explorer View and is used for many Sigasi features.
-
The actual UVM sources are still missing from our project. To include those, right-click the project name in the Project View and select New Linked Folder…. Navigate to
uvm-1.2/src
and click Select Folder. -
Now it’s time to configure the preprocessor. Right-click the project name again and select Open Preferences View. In this view, go to the Verilog Preprocessor Settings, where you can add Include paths.
- Add
src
to the include path and click the Add Include Path button to add a new empty text box. - Add the
sv
folder in the second include text box. - Now press the Apply button on the top right to reconfigure the project. This will rebuild the project.
- Add
After completing the steps above, have a look at the Problems count. While there were a lot of errors when the Sigasi project was initiated in step 2, applying the Preprocessor Settings should have resolved these errors. You should see at least one genuine validation message on the code.
To configure your own UVM project, you can follow the same steps if you start by opening your own project folder in VS Code.
See also
- How to setup a SystemVerilog UVM project in Sigasi (blog post)
- How to setup a SystemVerilog project in Sigasi Studio (blog post)
- ANSI and Non-ANSI Port Declarations in Verilog (blog post)
- Tips and tricks to optimize Sigasi Studio for VS Code (blog post)
- Documentation features for large designs in Sigasi Studio (blog post)