Setting up a regular SystemVerilog project in Sigasi Studio is easy. While UVM, the Universal Verification Methodology , complicates everything, Sigasi Studio simplifies that set up. In this blog post I will demonstrate how to use UVM in a Sigasi project.
As an example I will show how to open the UBUS project that is shipped with the reference implementation of UVM in Sigasi Studio.
The procedure consists of 10 simple steps:
- Download the reference implementation of UVM
- Unpack the sources on your disk (e.g. to
/Users/heeckhau/demo/uvm-1.2
) - Import the UBUS sources in Sigasi:
- Select File > Open Project from File System…, click Directory… and browse to the location of the UBUS source files (in my case this is
/Users/heeckhau/demo/uvm-1.2/examples/integrated/ubus
). - Click Finish
- Select File > Open Project from File System…, click Directory… and browse to the location of the UBUS source files (in my case this is
- Right click the project (
ubus
), and select Configure > Add (System)Verilog support - Make sure the project has a
Common Libraries
folder. If this folder is missing, right click the project and select New > Folder. Keep ubus as the parent folder and enterCommon Libraries
as the Folder name. Optionally you can select this folder to be a Virtual Folder under the Advanced » section. - Use your files system explorer (Windows Explorer, Finder, Nautilus) and navigate to the UVM sources (in my case this is
/Users/heeckhau/demo/uvm-1.2/src/
) and drag and drop this folder into theCommon Libraries
folder1 of theubus
project.
Select Link to file and folders and OK - Add the
uvm
sources to the build: right click onCommon Libraries/src/
and select Add to build (library work) - Add the UVM sources to the include path: right click the project and select Properties > (System)Verilog Preprocessor; enter
Common Libraries/src
as Include path and confirm with Apply and Close. - Open
examples/ubus_tb_top.sv
by double clicking the file in the project explorer. Notice the error markers on the`include
s. - Click on the error marker in the margin (with the small light bulb) and select Add sv to include paths. This automatically adds the
sv
folder to the include paths.
Your Sigasi Studio UVM project is now ready for use. Feel free to experiment with hovers, open declaration (F3), find references and autocomplete (Ctrl+Space).
Footnotes:
See also
- Setup a SystemVerilog UVM project in VS Code (blog post)
- How to setup a SystemVerilog project in Sigasi Studio (blog post)
- Wallpapers for Fans of Sigasi Studio (blog post)
- How to set up the UVVM Library in Sigasi Studio (blog post)
- How to use the new VHDL 2008 libraries in Sigasi Studio (blog post)