When you start using Sigasi, the first thing you have to do is Setting Up a Project. This consists of two steps: (1) selecting the VHDL files that you want in your project and (2) configuring in which VHDL library these files must be mapped. In most cases you already have this information in one form or another. For example in a makefile, in a Tcl simulation script, or in the project descriptor file of a third-party EDA tool.
Because there are so many different formats to describe this information, we cannot offer one universal solution. But to make the import process easier, we have developed Python scripts that make it easy for you to convert your own project description into a Sigasi project description.
The convertCsvFileToLinks.py script converts a CSV file (example file) into a Sigasi Project. This scripts adds a link to each file in the list and maps it to the corresponding library.
All scripts are open sourced under a BSD license. So you can freely customize them to your specific needs. Feel free to suggest or contribute improvements.
Of course we can help you write your scripts. send us an email for more info.
P.S.: You can also open files or projects with a script. Simply start Sigasi with parameter -p <path to your project folder>
See also
- Import a project in Sigasi Studio from `.f` files (blog post)
- Importing a Xilinx ISE project in Sigasi (blog post)
- Build systems for HDL projects (blog post)
- Importing a Quartus project in Sigasi Studio (blog post)
- Generating a Sigasi project from a Vivado project (blog post)