Sigasi Studio Preview (4.17)

Posted on 2022-07-14

For those users who want to get early access to the features and bugfixes of upcoming Sigasi Studio releases, we have set up an extra release channel, called Sigasi Preview.

The Sigasi Preview release channel offers more frequent releases than the official releases. This page gives an introduction to the most important changes.

Although these preview releases are less rigorously tested than the official releases, they are stable enough for daily use.

If you run into any problems, please let us know.

Current preview release

The changes since the Sigasi Studio 4.16 release are documented below

Documentation improvements

This release brings a slew of small documentation generation improvements.

  • Processes now show their associated comments
  • TOC items now have an li prefix to make it easier to hide these entries e.g. when hiding block diagrams through the following CSS, the TOC entries are also hidden div[id$=".blockDiagram"] { display: none; }
  • The content of extended identifiers is now sanitized (i.e. \<html>\) before inserting them into HTML
  • Correctly use td instead of th where necessary
  • [VHDL] Added protected type instantiations

New and Noteworthy Changes

  • Removed outdated documentation from Eclipse’s help pages
  • It’s now possible to disable the automatic wrapping in quotes or parenthesis of selected code
  • [VUnit] Run VUnit tests now only shows up when there are VUnit tests in the selected file
  • [VHDL] Added an autocomplete template for (others => '0')
  • [VHDL] Added support for aliasing to enums
  • [VHDL] Added a warning when assigning a string to an aggregate ((s1, s2, s3) <= "abc";)
  • [VHDL] Added a warning when using an incorrect range to constrain vectors or their initial values (constant a : std_logic_vector(-1 downto 0) := (-1 downto 0 => '1');)
  • [Verilog] Improved warning annotation for multiple design units in the same file on anonymous subprograms
  • [Verilog] Improved error message when Verible failed to format
  • [Verilog] Added checker instantiation autocomplete in checker constructs
  • [Verilog] Added the instantiation autocomplete in more contexts
  • [Verilog] Added the Anywhere context for custom autocomplete templates
  • [Verilog] Added an error when invoking a macro with arguments but no name ( `(x))

Bug fixes

  • Added icons to the Set Top Level dialog
  • Fixed error dialog when pressing Delete right before applying an autocomplete
  • Fixed rare racy CSV compile-order export
  • The info, warning, error, and Quick Fix light bulb icons are now consistent
  • Fixed rare error dialog during Checking Sigasi license
  • Made the our styling of tree views (such as Outline, Hierarchy, and Open Design Unit) more consistent
  • Made sure all Sigasi features work flawlessly after opening a recently closed project
  • Normalized the content of different type of design unit instantiations
  • Leafs in the Hierarchy View are no longer expandable
  • The filter for Open design unit (Ctrl+Shift+D) now correctly interprets * and ? and always searches for substrings instead of exact matches
  • [VUnit] Made sure that executed tests always show up in the VUnit View
  • [VUnit] The history of the VUnit View is now sorted chronologically descending
  • [VUnit] Added a checkbox in the history view to identify the current results
  • [VHDL] Fixed rare case where hovers didn’t show
  • [VHDL] Fixed false-positive Unused declaration for records when only elements of the record are used
  • [VHDL] VHDL keywords used in tool directives are no longer highlighted
  • [VHDL] Fixed recognition of generic package instantiations
  • [VHDL] Removed Quick Fix for adding a sensitivity list to empty processes
  • [VHDL] Fixed empty Hierarchy View when a formal is added twice in an instantiation
  • [Verilog] Instantiation autocomplete for design units using extended identifiers (\ext$ended" or \My!dentifier\) now works correctly
  • [Verilog] Removed enclosing instantiation for instantiation autocomplete
  • [Verilog] Fixed empty Class Hierarchy View when one of the classes in the hierarchy has no name
  • [Verilog] Fixed highlighting of numbers
  • [Verilog] Improved error marker range for incorrect preprocessor directives

Update or install?

You can download the stand-alone version of the latest preview from:

You can also update automatically when setting Preferences > Install/Update > Available Software Sites > Add… :

SHA sums (more info) can be checked via

System requirements

  • Sigasi Studio standalone is supported on:
    • Windows: Windows 10 (64 bit) or newer
    • macOS 11.6 Big Sur or newer
    • Linux: RedHat Enterprise Linux RHEL 7.7 (64 bit) or newer
      • Sigasi Studio depends on which can be obtained by installing libXScrnSaver
    • More information on supported OSes can be found on the Eclipse website
  • Sigasi Studio as plugin in your own Eclipse installation:
    • Eclipse 4.8 Photon up to and including Eclipse IDE 2022-03
    • Java JRE 11 or 17

We recommend at least 4GB of memory available for Sigasi Studio, and you need about 1GB of free disk space.


We welcome your feedback through the usual channels or the comments below. Note that comments are cleared after each official release.

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