This page deals with step three of using the Quartus integration plugin for Sigasi. We assume have already set up Sigasi as default editor in Intel Quartus.
Step three happens when you open a VHDL file in Quartus, and Sigasi kicks in to show you the file. There are several ways to open an HDL file in Quartus. The most common ways are: you can double-click a file in the Quartus project navigator, or double-click an error in the console log.
Sigasi will now start and find a workspace (the place where all of your Sigasi metadata lives). You can use the default workspace and tell Sigasi to keep using the same workspace from now on.
When you double-click a VHDL file, Quartus (as of version 12.1) opens Sigasi and passes three bits of information: (1) the file (2) the line number and (3) the project. The first time you open a file in a given project, Sigasi needs to import your project.
Also, the import wizard wants to know where Quatus is installed.
Sigasi mirrors the Quartus project, and so these mirrored projects are not regular Sigasi projects. In fact, the look really messy and confusing in the regular Project Explorer. We have created a special “Quartus project view” to look at the mirrored Quartus projects in Sigasi. When you import a Quartus project in Sigasi, the import wizard will ask you if you want to switch to the Quartus perspective. So: yes, you do want to switch to the Quartus perspective.
This is still a beta release, so we have some things that are not great yet. Please let us know what you like and what we should improve.
- When you open a file in Quartus, the Sigasi window may not snap to the foreground and get the focus. Most operating systems don’t allow windows to jump to the foreground as part of their malware protection. We’re trying to figure out a way around this.
- When you create a new file in Quartus (File > New… > VHDL File), Sigasi opens with a new file named @Vhdl1.vhd@, but the file is not added to the project.
- Importing a Quartus project in Sigasi Studio (blog post)
- VHDL Physical Type is not Synthesizable, or is it? (part 2) (blog post)
- VHDL Physical Type is not Synthesizable, or is it? (blog post)
- Installing Quartus on a 64-bit Linux system (blog post)
- List of known VHDL metacomment pragma's (blog post)