In earlier posts, I have explained that there are basically three ways of how to organize your VHDL code within your Sigasi environment. As a reminder:
- Aggregation of reusable projects (described in this article)
If you have a set of VHDL files, which may include packages, entities and architectures, we will call this a reusable project. The files are closely related and serve a single purpose. Often, these reusable projects take the form of an IP library (like the IEEE libraries), or an IP core (like a processor core or a memory controller). If you are working on large projects, such as a System on Chip (SoC) design, you are using IP cores.
*You can turn off the automatic builder while you are setting up your projects: Project > Build automatically. This will keep the compiler from starting before you have set things up correctly.*
In this blog post, we assume that one project is compiled in one VHDL library. You can easily adapt if you have several projects in the same library.
First, we need a project for
IEEE and for
STD. You could put those
in a single project, called
default libraries or something along those
lines. But I prefer to stick to the rule of one project for one library.
Just create a new VHDL project called STD, and remove the IEEE folders
from that project. Next create a project called IEEE and remove the STD
folders from that project. Now you need to make IEEE depend on STD:
Project > Properties > Project References and select STD as a
project reference for IEEE.
Now that you have the first two libraries, it is time to add your own
library. Select File > New > VHDL Project. Clear the
Use default location mark and select the location of your library.
Choose the library name (we’ll use
my_lib for this example) as your
project name and click Finish. Now, perform the following four
- Set the project dependencies: Project > Properties > Project References and select STD and IEEE as project references.
- Remove the virtual folder
Common Librariesfrom the
- Map the entire project to the correct library (
my_lib): right-click on the project > Library Mapping > New Library…
- If the project contains any stale VHDL files, unmap them. Right-click > Library Mapping > Unmap
- Compile the project (since the automatic builder is turned off): Project > Clean > Clean all projects and Project > Build.
As you add more and more projects, your projects will depend on each other too. Make sure you set the correct dependencies in step 1. You have to make project dependencies explicit in Sigasi. This may seem like a bit more work, but is also helps you keep a clean and clear project structure.
*Don’t forget to turn the autobuilder back on. Project > Build automatically*
This is a robust way of organizing large projects. Setting projects up takes extra time, say about half an hour for larger projects. Having separate reusable blocks in separate projects makes it easier to work in teams and to deal with third party IP.
If you are working on a serious industrial design, with reusable in-house IP and/or third party IP, we would recommend the one IP block per project approach. We especially recommended it for any mid or large scale project, or:
- If you have more than 5 VHDL libraries
- If you are using third-party code that you don’t want to modify
- If you are working on several designs with shared libraries and IP blocks
To show you an example of how to get started, I have created a video where I set up the first few libraries in the open source GRLIB collection. You can also download a zip file with all the GRLIB libraries (and a few of its example designs). Use File > Import… > General > Existing Projects into Workspace. Then Select archive file, Select All and click Finish. Importing and compiling everything will take a few minutes.