The Sigasi development environment allows a very large flexibility on how to organize VHDL projects. So much in fact, that it can become confusing. Let me outline three recommended ways of organizing your VHDL project.
(One not-so-recommended way, Organizing legacy projects, is useful if you are working with legacy projects whose files are scattered over many folders).
In this post, I’ll start with the simplest way of organizing: not organizing at all. In technical terms, we call this editing external VHDL files, because the files are outside of any projects.
There is no set up required. You just open the VHDL file you want to edit. Either click File > Open File… or drag a VHDL file from your file browser to the edit area.
The good part of “no organization” is that you don’t have to organize. There is no set up time and you can get started viewing and editing a VHDL file in a matter of seconds. On the down side, several interesting features won’t work:
- No errors when you use an undeclared name.
- Any name you use that is declared in another VHDL file will be treated as just that: a name. This means the following features cannot work for these names:
- rename refactoring
- semantic coloring
- jump to declaration
If you open several VHDL files using this external files method, Sigasi will try to link them together. So some features might work, depending on how which VHDL files you have opened.
We suggest you use the single VHDL file mode for quickly looking at a file and for making small changes. If you are going to work seriously on your project, we suggest you use one of the two other methods.
- One design in one folder (blog post)
- One IP block per project (blog post)
- Sigasi Keyboard shortcuts Cheat Sheet (blog post)
- Export a VHDL project to an archive file (blog post)
- The magic of Sigasi's type-time compiler. Part 2: Builder (blog post)