.f) files are a ‘de facto’ standard for exchanging project
information between EDA tools and managing HDL files in bigger FPGA
and ASIC projects. In this article we discuss the
.f file format,
its limitations, and how to use it to create a Sigasi Studio project
from your HDL code and
.f files contain a list of command line options for an EDA tool,
often an HDL simulator. The
.f extension originates from the fact
that these command line option files are specified on the command line
-f option, as in
$ my_eda_tool -f file.f
In other words,
.f is hardly a file format.
.f files contain a
collection of (usually UNIX-style) command line options. As options
are EDA tool and EDA vendor dependent,
.f files may be generated for
specific EDA tools, and may contain different information depending on
the tool for which they’re intended. EDA tools that generate
files for other tools may in fact generate a set of
e.g. one for each popular simulator.
Still, there is enough commonality between
.f files to handle them
as a file type.
.f files contain the following elements:
- file names of the design files, optionally with wildcards (
- options starting with a dash, like
- options starting with a plus, like
- comments: lines starting with
!or text enclosed in
- lines may be concatenated with the continuation character
- entries may include environment variables
.f files are just a collection of file names, while others
contain other elements as well. Parsing of these files is not
particularly difficult, but, as mentioned, the semantics may be
different depending on the tool for which they’re intended.
.f files have some limitations when they’re used to
capture project information.
First of all, they’re meant to be used with a particular tool, so any project information which is irrelevant to this particular tool is not included.
A number of tools, e.g. some simulation library compilers, may need
multiple runs to compile an entire project because each compiler run
can only handle one design library. This is mainly the case for VHDL
projects, because (System)Verilog projects usually use one single
library. In such case, a
.f file may only contain files associated
with one library, and the library name may not even be present in the
Also further information, e.g. the VHDL or Verilog language version,
may or may not be present in a
Well, actually, that’s probably because no vendor-neutral format exists to communicate HDL project information between EDA tools. Despite the limitations, it’s one of the few things that exist to save design engineers from creating and maintaining a collection of in-house scripts (often in a polyglot of tcl, perl, shell scripts, python and maybe other languages) for that purpose.
A further plus is that
.f files are text files, so they’re human
readable and easy to generate and to parse. And finally, any missing
information in a
.f file may conveniently be added on the command
$ my_eda_tool -f file.f --other-option ...
Sigasi offers support for
.f files in the open-source Sigasi
Project Creator .
This tool is written in Python and Antlr, and may assist you with
setting up a Sigasi Studio project from one or more
.f files. Sigasi
Project Creator is offered under a BSD
Sigasi Studio users are welcome to contact us for support .
Your contribution to improve the Sigasi Project Creator is also
So far, the Sigasi Project Creator supports:
- input files (mapped to library work)
+incdir+...(Verilog includes, added to Verilog preferences)
+define+...(Verilog defines, added to Verilog preferences)
-makelib <libname> ... -endlibwith input files on separate lines between makelib and endlib, with continuation characters (mapped to the library
<libname>, or the part of libname after the last slash (
/) if it contains any)
-f <filename>to include another
- environment variables in input files and include paths (which get expanded if they are defined)
- VHDL, (System)Verilog and mixed language projects
- multiple top-level
python -m pip install -r requirements.txt
Finally, go to the directory which will be your project root and run
the Project Creator. For simple projects, any
.f file should
work. For more complex projects with different libraries and include
.f file should be chosen which preferably has the relevant
information, e.g. a
.f file for Cadence IUS.
python /my/path/SigasiProjectCreator/src/createSigasiProject.py projectname path/to/my.f
Further command line options of
createSigasiProject.py are discussed here .
After this, you should see two new files and a folder in your current
You can open the project in Sigasi Studio using File > Open Projects from File System…. Click Directory…, select the project directory, then click Select Folder and Finish to open the project.
Some errors may remain due to e.g. missing library or (System)Verilog
include path information in the
.f file. Sigasi Studio will help you
resolve the errors. The library mapping can be
the Project view. Missing include paths may often be fixed using a
quick fix. With little or no further
effort, your project is fully set up.
- Importing a Quartus project in Sigasi Studio (blog post)
- Scripting Sigasi project creation (blog post)
- Generating a Sigasi project from a Vivado project (blog post)
- Importing a Xilinx ISE project in Sigasi (blog post)
- Build systems for HDL projects (blog post)