I have blogged before on how to import Xilinx ISE projects in Sigasi before (Importing a Xilinx ISE project in Sigasi). In this blog post I show how you can import an existing Vivado project into Sigasi.
If you have a Vivado project which uses one or more IP cores, the project becomes complex quickly. Vivado generates different sources for Simulation and Synthesis. And although VHDL has elegant support for this –entities can have multiple architectures–, Vivado generates duplicate entities instead. This forces you to switch between two complete different views on your project. If you have multiple IP cores this is really annoying.
To make it easier to use Sigasi in combination with Vivado projects, we added a Vivado tcl script to our SigasiProjectCreator Github project . This Vivado tcl script creates a list of all HDL source files in your Vivado project and writes this list together with the HDL library name to a CSV-file. This CSV-file can be converted to a Sigasi project with the createSigasiProject.py script:
The following command assumes you’re in a Command Window / Terminal and
vivado is in your path.
You can also run the script in the TCL console of a Vivado GUI session if you source the script there.
vivado -mode batch -source ~/git/SigasiProjectCreator/src/SigasiProjectCreator/convertVivadoProjectToCsv.tcl project_1.xpr
This TCL scripts creates a file
vivado_files.csv which contains a list of VHDL and Verilog source files and their library information.
When you inspect the source of this TCL script , you will see that we filter for Simulation source files only.
You can switch to synthesis by replacing
python3 ~/git/SigasiProjectCreator/src/createSigasiProject.py project_1 vivado_files.csv
This script generates the
.library_mapping.xml files that define the Sigasi project.
Note that you might need to update the
PYTHONPATH as explained in the README file .
When you make changes to your Vivado project, you need to re-run this script. Take care that you also regenerate the VHDL and Verilog sources of your IP cores when you make changes. Vivado does this lazily.
Note that Sigasi cannot decrypt the encrypted Xilinx IP cores. For some IP cores, even the interface (for example, the entity declaration) is encrypted. Since we do not have permission to decrypt this, you may see some unknown declaration errors in your designs.
- Importing a Xilinx ISE project in Sigasi (blog post)
- Import a project in Sigasi Studio from `.f` files (blog post)
- Importing a Quartus project in Sigasi Studio (blog post)
- Scripting Sigasi project creation (blog post)
- Common error from XSim with XPM library (blog post)