Presentation by Titouan Vervack at EclipseCon France 2017 on 2017-06-21.
See also
- Taming complex chip designs with beautiful diagrams (blog post)
- VHDL 2017: new and noteworthy (blog post)
- VHDL generation from Yakindu state charts with Xtend (blog post)
- How to set up the UVVM Library in Sigasi Studio (blog post)
- Using Sigasi Studio's Graphics Configuration (blog post)