Export a VHDL project to an archive file

Posted on 2009-10-19 by Hendrik Eeckhaut
Tagged as: hdt-2.0howto

If you want to mail a Sigasi VHDL project to a colleague (or to support), you can easily archive your project within Sigasi itself.

Just right-click on your project in the project explorer and select Export…

Next select Archive File

In the third and last step, you can exclude some files from the archive. Make sure you include the vhdl source files and the .project and .library_mapping.xml files, since these contain the necessary project information.

In this step you can also select some extra options (e.g. choose between tar and zip).

You also have to specify a name for the archive.

That is it.

If you want to mail your project to support, do not forget to add the log file, and the external libraries to your mail.

See also

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