Of course, he wanted his students to simulate before they synthesize. I thought it would be nice to have a module that can emulate a this a seven-segment display as ASCII-art.
I created this module in about an hour and after some more minor modifications, I decided to publish it for everybody to use.
- Copyright policy of IEEE (opinion)
- Why can't HDL designers live without block selection mode? (opinion)
- Four (and a half) ways to write VHDL instantiations (blog post)
- VHDL 2019: Conditional Analysis (blog post)
- VHDL 2019 Conditional Analysis (screencast)