This page explains how to install and configure the Sigasi Studio extension for VS Code.
Requirements
VS Code Version
The extension requires VS Code or VS Codium version 1.77.0 or higher.
Java Runtime
The path to use the Java Runtime (JRE) can optionally be configured in the settings.
If the setting is empty, the extension will extract the included JRE in the user’s home folder.
To install the extension, open the Extensions pane using Ctrl+Shift+X.
In the Search field on top, type Sigasi.
Click the Sigasi extension and click Install.
The settings for the Sigasi extension can be reached trough:
Open the Command Palette using Ctrl+Shift+P
Start typing and select Preferences: Open Settings (UI)
In the Search field on top, type Sigasi.
First, configure the Path To License. This can be a local node-locked license file or a floating license server (e.g. 27000@myserver.example.com). The setting for the license path is similar to the one in Sigasi Studio on Eclipse.
Optionally, configure the JRE location in Sigasi > Java: Path. Make sure to add the java executable name in the configured value.
Alternatively, the Sigasi extension settings can be accessed through the Manage icon () in the extensions overview.
Talkback
You can help improve the Sigasi extension for VS Code by enabling the automatic submission of usage statistics and error stack traces.
More information about this feature is available on the Talkback manual page.
This feature is disabled by default.
To enable talkback in the VS Code extension, open the settings and enable the Sigasi: Enable Talkback option.
The messages sent to Sigasi can also be logged locally. Then you can view these messages using the Sigasi: Open Talkback Log command.
In order to log the messages locally, a data storage needs to be configured.
On Disk Caching
You can specify a directory to be used by the Sigasi Language Server to write the cache and talkback logs to.
Open the settings and search for Sigasi › Server > Caching: Data Location.
The directory needs to exist already.
Choose a local folder for optimal performance.
Once you’ve configured this directory, the setting Sigasi > Server > Caching: Enable On Disk Caching can be enabled.
The cache will speed up the plugin by preserving the state from an earlier moment.
This will speed up the build significantly.
Be careful though: opening the same project in another VS Code window at the same time will corrupt the cache causing a myriad of issues.
Sigasi Studio is distributed online. It is available in two versions: as a
stand-alone application or as a plugin inside a standard Eclipse
installation. Your license gives you the right to use either version, at
any time, at your discretion. Therefore, your first task is to decide
which version suits your requirements, based on the description below.
Depending on the chosen version, you should then follow the
corresponding installation instructions.
Sigasi Studio App
The stand-alone application has the following characteristics:
Recommended if you are not using Eclipse yet
Installation is trivial: just unzip!
Everything is included in a single download
Well-balanced set of features
Optimized for VHDL and Verilog development
Complete freedom to add and configure plugins
Sigasi Studio Eclipse Plugin
The Eclipse plugin has the following characteristics:
Can be useful if you are using Eclipse already
Easily plugged into your existing Eclipse platform
Complete freedom to add and configure plugins
Over one thousand other Eclipse plugins to choose from
Support for C, C++, Tcl, and other languages
Support for many version control systems
When updating an existing installation, you need to extra care to diasble the
option Contact all update sites during install to find required software.
Not doing so might break your installation.
Sigasi Studio Custom Installation
Recommended for (larger) teams
Automates the setup of Eclipse, the Sigasi Studio plugin, and your project
Ensure that team members have a uniform setup
Quickly set up Eclipse with Sigasi Studio
Configure team preferences during setup
Check out a project from version control at setup time
Optionally add support for other programming languages
To download and install Sigasi Studio as a stand-alone application, follow the
online Installation Instructions.
After downloading, choose or create a folder where you want to install
the software and unpack the archive there. The archive contains a
single top-level folder called sigasi. Inside the folder, there is an
application startup file, also called sigasi. Start the application by
executing this startup file.
If you are using RedHat Linux 6 or CentOS 6, you need to follow the Plugin installation
instructions as explained here.
Running Sigasi Studio with multiple users on the same server
The following section is only relevant if you’re using a Sigasi Studio version older than Sigasi Studio 4.17.2.
Starting with Sigasi Studio 3.8, the Sigasi launcher listens on port 4444. To avoid conflicts on this port when Sigasi Studio is used on a server with multiple users concurrently, the following changes need to be made:
Edit sigasi/configuration/config.ini and replace eclipse.application=com.sigasi.runner.open with eclipse.application=org.eclipse.ui.ide.workbench
In sigasi/sigasi.ini add following lines between @noDefault and -vmargs:
--launcher.defaultAction
openFile
If there are other arguments between @noDefault and -vmargs, append to these.
This way Sigasi Studio uses the default Eclipse behavior instead of the custom Sigasi runner.
More information on the Eclipse OpenFileFeature can be found here.
The Sigasi runner allows you to open projects using the -p option.
This is not possible when using the default Eclipse runner.
Installation of Sigasi Studio Eclipse Plugin
There are two ways to install the Sigasi Studio Eclipse Plugin:
You can check your Java version with java -version
Java can be downloaded from several sources, a.o. Adoptium.
Prerequisites: Eclipse
You need to have at least Eclipse version 2021-03 (4.19).
This Eclipse version and the Sigasi Studio plugin require Java 11 or 17.
If you don’t have Eclipse installed yet, the C/C++ flavor would be a good place to start. Just download (Windows 64 bit/Linux 64 bit/Other versions), unzip, and start.
This requires the host where you install the Sigasi Studio Plugin to have access to our download server.
After starting Eclipse:
Click Help > Install New Software….
In the Work with: field enter https://download.sigasi.com/sigasi-studio/updates/studio and press enter.
Check the checkbox next to Sigasi Studio.
Since Sigasi Studio 4.15, installing Sigasi Studio optional features is no longer recommended.
You must disable the option Contact all update sites during install to find required software when installing the plugin.
Click the Next button.
The following steps are pretty self-explaining.
After the installation, you will need to restart Eclipse. Once this is done, go to Window > Perspective > Open Perspective > Other… and select the Sigasi Perspective. You can then close the Welcome View to show the Sigasi Views.
Installing the Offline Update Site
Installing the offline update site is very similar to installing from the main update site, where step 2 is replaced with these steps:
Download the offline update site
In the Install Wizard, click Add…
Click Archive…, browse to the zip file you downloaded, and confirm with OK.
Next, continue with step 3. in the general eclipse installation instructions.
It is recommended to disable the option Contact all update sites during install to find required software
when installing update sites.
GPG Certificate Validation
Eclipse 4.26 (2022-12) added GPG certificate checking capabilities. When you install new plugins, you will be prompted to trust any not-yet-trusted GPG keys or unsigned artifacts. Because Sigasi artifacts are correctly signed using GPG, you can expect to see the following screen the first time you install or update Sigasi in an Eclipse >= 4.26.
Previously trusted keys can be inspected by going to Window > Preferences > Install/Update > Trust.
You can refer to this page for all information regarding GPG at Sigasi.
Licensing
The license key can be filled in under Window > Preferences > Sigasi > License Key.
More details can be found here. The license unlocks the features for your edition.
Configuration
Sigasi Studio stores its projects on the file system in one or more
workspaces.
When you start the tool for the first time, it will propose to create a
workspace for you:
Although you can work with multiple workspaces, we recommend using a
single workspace for all your projects.
Software Updates
Sigasi Studio has an automated update system. When updates are available, you
are notified by a pop-up window called Updates Available in the
bottom right corner:
If you want to install the updates, click anywhere in the pop-up window.
After a few seconds, a new window will appear with further instructions.
The updates can be postponed by closing the pop-up. You can perform the
updates at any time by clicking the
-icon in the status bar
at the bottom of the screen.
It is good practice to first create a backup of your installation folder before running an update. This can be done by simply compressing the eclipse or the sigasi folder in an archive (zip file)
Update Sigasi Studio App
If you run Sigasi Studio as a standalone application, the automated update system will periodically check for software updates.
Update Sigasi Studio Eclipse plugin
If you run Sigasi Studio as an Eclipse plugin, you may need to check for updates manually, by clicking Help > Check for Updates.
You can enable automatic updates by opening this preference page: Install/Update > Automatic Updates. Next, enable Automatically find new updates and notify me. Feel free to modify any of the available options.
Firewalls and Proxies
If the updates are not automatically fetched from the Sigasi Studio update server you are probably behind a firewall or proxy server. You can configure Sigasi Studio’s proxy settings in Window > Preferences > General > Network connections.
Make sure to set the Active Provider to Manual and configure the appropriate Proxy entries.
Whether you need to configure the entries for HTTP or HTTPS depends on the Locations configured in the Available Software Sites settings.
If you can not add a firewall exception for our update site, the fallback solution is to download the complete application from our website.
You can completely replace your old installation; all settings are stored in your workspace (the default is workspaceSigasi in your home directory).
Your work with Sigasi Studio is typically organized as a project. A project
is a collection of VHDL and/or Verilog/SystemVerilog files that belong together. Sigasi Studio
understands the HDL units defined in the files and the relationships between them.
Your first step is to set up a project. There are several ways to do this.
The most common ways are:
Note that while you initially need to choose between a VHDL and a Verilog/SystemVerilog project, any Sigasi Studio project can be a mixed language project.
If you wish to create a mixed language project, we recommend importing or creating a VHDL project and then adding the Verilog/SystemVerilog support to this project.
To create a mixed language project, right-click your project and select Configure > Add VHDL Support or Configure > Add Verilog/SystemVerilog Support as needed.
Features
In projects, you can navigate from instantiation statements to the matching entity or module.
This also works in mixed language projects.
You can navigate from VHDL entity instantiations in Verilog/SystemVerilog code and to Verilog/SystemVerilog module instantiations from VHDL code.
You can also open the declaration of ports and generics/parameters in mixed instantiations.
Other supported features:
Find references for entity names, modules, ports, generics, and parameters.
Autocomplete Verilog/SystemVerilog module instantiations in VHDL code and VHDL entity instantiations in Verilog/SystemVerilog code.
Error reporting of incorrect entity names, modules, ports, generics, and parameters in instantiations.
You can import an existing VHDL or Verilog/SystemVerilog project from the file system by clicking
File > Import… > Sigasi > Import a VHDL project or Import a (System)Verilog project. Browse to the
root directory of the project, and press Finish.
2: Set Libraries (VHDL or Mixed)
Since Sigasi Studio 4.4, Sigasi Studio automatically configures libraries of imported projects, based on project information
such as library and use clauses. If you need to customize the library configuration, you can assign different
libraries to your files and folders. Right-click on a file or folder and select Library Mapping > New Library….
Then fill out the correct library name.
If you need additional files that are not in the project root directory,
just drag them from your file browser into the project. You will have
the option to create a link rather than copying the files.
Note 1: dragging files works on Windows (using Windows Explorer), and
on Linux (using Gnome Nautilus). If you use KDE, you should install Nautilus.
Note 2: to avoid absolute paths in the .project file, environment variables can be used.
Right-click the file or directory in the project explorer and select
Properties > Resource > Location > Edit… to configure the path of the resource.
To access environment variables, you have to prefix the environment variable with ENV-.
For example: to refer to the home directory you can use ENV-HOME.
Creating a new, empty project
To create a new project, select File > New > VHDL Project or
File > New > Verilog Project. Then give your project a name.
By default, the Use default location checkbox is checked, which
means that new projects will be located in the workspace folder.
Alternatively, you can uncheck the checkbox and choose an arbitrary
location for your project. This is especially useful if you want to use
Sigasi Studio with an existing design.
You can also select the VHDL version or the version of .v files.
After creating a new project, you can add existing files by dragging
them from your filesystem into the project explorer. New files can be
added by clicking File > New > VHDL File, File > New > Verilog File,
or File > New > SystemVerilog File.
Other ways to set up a project
Adding VHDL or Verilog/SystemVerilog support to an existing Eclipse project
You can also add VHDL or Verilog/SystemVerilog support to any project in your
workspace by right-clicking the project in the project explorer and
selecting Configure > Add VHDL support or Configure > Add
Verilog/SystemVerilog Support. You can also remove VHDL or Verilog/SystemVerilog
support from Sigasi Studio projects by selecting Configure > Remove VHDL Support
or Configure > Remove Verilog/SystemVerilog support.
Note that with a Sigasi Studio XL
or a Sigasi Studio XPRT
license, you can have mixed VHDL and
Verilog/SystemVerilog support at the same time.
Importing a project from an archive
Sigasi Studio projects can be shared using file archives. All project-related
settings are stored in two hidden files in the project folder.
Therefore, you can create an archive of the entire top level folder
(File > Export > General > Archive file) and send it to someone
else.
You can import a project from an archive by clicking
File > Import…> General > Existing Projects into Workspace
and selecting Select archive file. Browse to your project archive
and press Finish.
Programmatically creating a project
The Sigasi Studio .project and .library_mapping.xml files can be created using code from our
publicly available Sigasi Project Creator project.
The project offers Python classes that make it easy to generate a Sigasi Project from your own project
specifications.
For more information and examples, check out the Sigasi Project Creator project on GitHub.
Deprecated Features
Note that resource filters are discouraged in Sigasi Studio for Eclipse and unsupported in
Sigasi Studio for VS Code and Veresta.
You can request a 7-day trial license from within Sigasi Studio for Eclipse and VS Code and quickly start working on your HDL project.
Sigasi Studio for VS Code
When you install the extension from the VS Code extension marketplace and open your HDL project, you will see a small pop-up window on your bottom right with a button that says Request trial.
After clicking it, a trial request form will appear. Note that the MAC address will be pre-filled, but you should make sure to select the correct one for your machine.
When the form is completed, press Submit and you are good to go. If the process is successful, an email will be sent to the provided address to confirm your identity and your license file will be sent to you via a second mail with instructions on how to install it.
Note that if you missed the original pop-up, you can get to the trial form by clicking here in Sigasi > Path To License setting.
Sigasi Studio for Eclipse
Similar to Sigasi Studio for VS Code, you can request a trial from within Sigasi Studio For Eclipse.
Download the executable from our website and open the trial form by clicking Try on the welcome page.
You will also notice the MAC address is pre-filled here.
When the form is completed, press Submit and check your email to confirm your identity and a second email containing your license and instructions on how to install it.
HDL libraries are a very powerful feature of the HDL languages. Sigasi Studio
makes it easy to configure and use them. In this chapter, we assume that
the basic concepts of HDL libraries are understood. We will explain how
they are implemented in Sigasi Studio.
Like with any HDL tool, Sigasi Studio needs to know where the libraries are
located on the file system. We will describe how the library
configuration can be examined and modified using the GUI.
We will also present some use case about how to set up libraries with
Sigasi Studio to organize your projects.
Examining the library configuration
You can examine the library configuration in the Libraries View
and in the Project Explorer view. The Libraries view shows how
design units are mapped. The Project Explorer view show how VHDL or
SystemVerilog files are mapped.
In the Libraries view you can see a tree of all libraries in your
projects. You can open each library to see all contained design units as well as their description style.
In the Project Explorer view each physical file or folder is annotated
with the library it belongs to, between square brackets:
What you see here is the initial library mapping of a demo project (you
can create such a project by selecting File > New > Other > Tutorial
VHDL Project or Tutorial SystemVerilog Project).
In the screenshot we see a project called Demo, with a folder named
Common Libraries. In that folder, you see the typical standard
libraries (std and ieee) upon which all VHDL projects depend. The
demo project itself consists of a few VHDL files.
Next to the project’s name Demo, is the annotation work. This means
that, barring any overrides, everything in the project will be stored
inside the work library.
Lower down, we see overrides. For example, the STD folder has an
annotation std. This means that, again barring any further overrides,
the entire contents of the STD folder will be mapped into the library
std. There are no limits to the number of overrides that can be
performed. If this needed, any individual file can be mapped to a
separate library.
Modifying the library configuration
The library mapping for project files can be modified in the Libraries
and Project Explorer view.
Select a file or a folder in the Project Explorer and right-click.
You get a Set Library context menu, with a number of options:
Select Exclude from build to exclude the file or folder from any library
Select New Library… to define a new library and map the file or folder to it
If one ore more folders are selected, the folder can be added to a library with the folder name(s)
Select the name of an existing library to map the file or folder to that library
When you map a file into a library, only that file is affected. However,
when you map a folder into a library, then everything in that folder
will be mapped into that library. Any overrides in the folder and its
sub-folders will be removed. When you are defining the library mapping
for a new project you should map from top to bottom.
So in the case of our Demo project, you would change (if work is not
a good default) the top folder’s mapping first and then override the
mapping in the sub-folders.
When you are changing the library mapping of a project, the project will
be rebuilt completely. In order to avoid several consecutive rebuilds
while you are setting up your libraries, you can temporarily disable the
automatic rebuilds, until you are finished setting up your library
mappings. You can do this by disabling the Project > Build
Automatically option.
To exclude a file from all libraries, the library mapping context menu
provides an Exclude from build option. You can apply that to any file or folder in
the project. Sigasi Studio will then assume that the corresponding resource is
not a part of the project and will not include that resource in a
project build. This is typically useful when you have stale copies of
HDL files or folders lying around that you want simply to be ignored.
(System)Verilog include files
(System)Verilog include files are always excluded from the build. Any
file that is included in another design file gets excluded from the
build, even if it has an extension that would normally identify it as
a design file, e.g. .v or .sv. It often doesn’t make sense to
compile include files by themselves. Instead, include files are
compiled in the context of the file in which they are included.
Configuration file
All library configuration information is stored in the .library_mapping.xml
file in the root of your project.
If you edit this file, your project will be cleared and rebuilt automatically
(a so-called Clean Build).
Sigasi Studio only writes changes to this configuration file when you make
changes to the library configuration with the context menu in the
Project Explorer.
When you do make changes, Sigasi Studio first checks that all paths in the
library configuration still exist. If a path no longer exists, it will be
removed from the configuration file.
Note that the library configuration file is case-sensitive, even on Windows.
Library configuration warnings and Quick Fix
If the library mapping file contains invalid entries, there will be a warning on the .library_mapping.xml file.
This warning will show in the Project Explorer, in the editor and in the Problems View.
An associated Quick Fix is available through the Problems View.
When invoked, it will remove all invalid entries from the .library_mapping.xml file.
Common Libraries
Each project has a folder called Common Libraries.
This is where reusable libraries go: either vendor libraries, third party IP
libraries or your own reusable libraries. By default, the STD and IEEE
libraries are added to this folder.
The Common Libraries folder behaves like any other folder.
You can delete it, rename it and apply a different library mapping.
In most cases, however, the default configuration is just what you need.
If your project doesn’t have a Common Libraries folder, you can just
create it by right-clicking the project in the Project Explorer and
selecting the New > Folder dialog. In the New Folder dialog,
select Advanced and Virtual Folder and name the folder Common Libraries.
How to add files to Common Libraries?
In any newly created VHDL project, the Common Libraries folder
contains the VHDL files of the IEEE and STD libraries.
To add files to the Common Libraries folder, locate a folder with VHDL files
on your file system using the Project Explorer or the file explorer of your OS
and drag the folder with VHDL files to the Common Libraries folder.
Alternatively, you can right-click the Common Libraries folder and select the
New > Folder dialog where you can use the Advanced » settings to create
a Linked Folder pointing to the actual folder location that contains the
files you wish to add to the Common Libraries.
How is Common Libraries different from another folder?
Common Libraries by default is a virtual folder. This means that it is not
a real folder in the project directory and it can only contain references to
folders on your file system.
Files in Common Libraries are supposed to be error free. Sigasi Studio
will not mark errors or warnings in these files.
Next to these, a few other libraries’ errors and warnings are never marked, regardless of their location.
These libraries are: std, ieee, altera_mf, altera, XilinxCoreLib, unisim, mentor, lpm, simprim, std_developerskit, unimacro, and modelsim_lib.
While you work on your project, you don’t want to edit the files in the
Common Libraries, but you need them to compile your project.
If you activate an external compiler,
files in Common Libraries are supposed to be pre-compiled. If you tell
Sigasi Studio to compile your project using an external compiler, the
Common Libraries are skipped. You need to pre-compile them yourself and let
your compiler know where the compiled libraries are. For ModelSim, you can
use the “modelsim.ini” file for this. If your project root contains a “modelsim.ini”
file, it will be used instead of the default “modelsim.ini” file.
Pre-compile Common Libraries
This section links to various recommendations on to pre-compiling the simulation models of external libraries in the Common Libraries, depending on the external compiler.
You don’t need to pre-compile VUnit libraries for running
VUnit tests. The VUnit framework compiles its own library when needed.
If you’re using libraries like OSVVM, you need to call
add_osvvm() in run.py to tell VUnit to also compile the OSVVM
library.
Further documentation on using VUnit in Sigasi Studio is available
here.
External compiler in a VUnit project
If you want to configure an external compiler in a VUnit project
(e.g. for additional syntax checking), you need to ensure that the
compiler has the VUnit library. Otherwise, the compiler will flag all
VUnit constructs in your HDL code as errors.
This script
demonstrates how to compile and enable the VUnit library for Modelsim
and Questa. Run this script in the folder where you want to install
the compiled VUnit library. This should be outside your project
folder. The script takes the path of your VUnit installation as a
parameter. Once the compilation is finished, go to your project
folder and run these commands:
vmap -c # only if your project folder doesn't contain modelsim.ini alreadyvmap <folder_where_the_script_ran>/vunit_lib vunit_lib
Note that the OSVVM library is shipped with Modelsim, so you won’t
need to compile it yourself.
For other external compilers, a similar approach is needed. Customers
who need help with that are welcome to contact
support.
What if I broke my Common Libraries folder?
If you have modified the Common Libraries folder, you can always
revert it back to the original state.
Right-click on the Common Libraries folder of your project in the explorer
view and apply menu-entry Set Library > Reset Common Libraries.
Resetting the library mapping
Sigasi Studio contains two functions to reset all or part of the library mapping.
Reset Common Libraries updates the common VHDL libraries to the
version (‘93, ‘2002, ‘2008, ‘2019) required by your
project. User-defined common libraries remain untouched. To
access this function, right-click the Common Libraries folder
inside your project in the Project Explorer and select Set
Library > Reset Common Libraries.
Reset Library Mapping resets the entire library mapping of your
project. After resetting the library mapping, Common Libraries
are reset as above, and all design files are mapped to library
work. Note that this action cannot be undone, so only use it
when you want to rebuild the library mapping from scratch. To
access this function, right-click your project in the Project
Explorer and select Set Library > Reset Library Mapping.
Sigasi Studio allows you to share libraries between multiple projects. The
easiest way to do this, is to develop each library in a separate project
and configure the Project Dependencies accordingly. To configure the
project dependencies, right click the project (the one that uses the
shared library) and select Properties. Next click Project
References and mark the library project as referenced project.
Using third party libraries
Many projects use third party libraries. These can be added to the
project as any other set of VHDL files.
A number of popular third party libraries are the following:
Vendor
Library
Install dir example
AMD/Xilinx
unisim
C:\Xilinx\Vivado\2020.1\data\vhdl\src\unisims
AMD/Xilinx
unimacro
C:\Xilinx\Vivado\2020.1\data\vhdl\src\unimacro
AMD/Xilinx
XilinxCoreLib
C:\Xilinx\14.4\ISE_DS\ISE\vhdl\src\XilinxCoreLib
AMD/Xilinx
xpm
C:\Xilinx\Vivado\2020.1\data\ip\xpm
Intel
altera_mf
C:\Intel\17.0\quartus\libraries\vhdl
Mentor
modelsim_lib
${ModelSimPath}\vhdl_src\modelsim_lib
Aldec
aldec
C:\Aldec\Riviera-PRO-2015.02\vlib\aldec\
On Linux the default installation location for AMD/Xilinx software is /opt/Xilinx.
XilinxCoreLib is a very big library with more than a thousand entities and
architectures. If you include all of these design units, it slows down the
compilation phase of Sigasi Studio. In order to avoid that, Sigasi Studio
only adds the packages with the component declarations to your project by
default. It excludes the entities and architectures from compilation.
You can easily add selected entities (and architectures) to your project by
right clicking the corresponding file (filename = entity name.vhd) in the
Project Explorer, and selecting
Set Library > xilinxcorelib.
Library errors from external compilers
If you are using the External Compilers, the external compiler
can also put error markers on library clauses. You can easily verify this by
checking the prefix of the error message (e.g. vcom: for vcom errors).
Consult the Libraries section of the external compiler
integration for more information on configuring libraries for your external
compiler.
The extension will start once a .project file is detected in the root of the open folder.
The project settings and library mappings are compatible with SiStE
.
See the Setting Up a Project and Libraries manual pages for all details.
If you’re familiar with Eclipse Resource Filters, note that these are not supported by VS Code and will be ignored if there are any filters in the .project file extension.
To change library mappings, you can use the right-click menu in the Project View and select Set Library as shown in the image below.
Then you can select an existing library or choose New Library… to type a new library name.
Once you type a new library name, the file/folder you selected will be added to the library you created.
If you want to add a file/folder to an existing library, you can choose one of the existing ones from the list (such as work).
If you want to exclude files/folders from a Sigasi project, select Exclude from Build. When you do this, that file or folder (along with its contents) will no longer be used in your project.
Note that the excluded resource(s) will still be visible in the Project View and you can still add them (Set Library) to the project.
Creating new libraries, adding a file/folder to an existing library, or excluding files/folders from build will modify the .library_mapping.xml file in your project.
VHDL and Verilog Version
To change the VHDL or Verilog version, you can right-click on a project, folder, or file in the Sigasi Project View and click Set Language Version.
Then select whether you want to set the VHDL or Verilog version. If you only see one of the two, you might need to add language support. Finally, select the version you want.
Language Support
To add or remove language support, you can right-click on a project from the Sigasi Project View, click Configure, and Add/Remove VHDL or Verilog/SystemVerilog Support. This will enable or disable language preferences among others.
Workspace
To add a new project to your workspace, press File > Add Folder To Workspace.
Make sure the project you’re adding has a valid .project file.
Environment Variables
Sigasi Studio supports environment variables in its project configuration.
This helps to avoid absolute paths in the .project file.
To use environment variables, you have to prefix the environment variable with ENV-.
For example: to refer to the home directory you can use ENV-HOME.
Custom Project Variables
Some variables are automatically defined.
PROJECT_LOC with the PATH of your project
PARENT-<COUNT>-<VARIABLE> which points to COUNT levels above the PATH of the VARIABLE
For example, if your project lives in /design/projects/project1, then PARENT-2-PROJECT_LOC/companylibrary points to /design/companylibrary.
You can also use custom project variables, e.g. VUNIT to point at your VUnit installation.
You can configure these variables as follows:
Press Ctrl+Shift+P to open the Command Palette
Select Preferences: Open Settings (UI)
In the Setting tab, navigate to Extensions > Sigasi > General > Custom Project Variables
Add variables and their values as required
Note that custom project variables can be set on the User level, and also per Remote or for a specific Workspace.
Sigasi Studio is built upon the Eclipse platform, which permits to use multiple languages within a single environment. The user interface can be customized for a particular language. In Eclipse terminology, this customized user interface is called a perspective. The icon and name of the current perspective is highlighted in the upper right corner.
Sigasi Studio provides a Sigasi perspective to work with both VHDL and Verilog files.
If you use the standalone version of Sigasi Studio, this perspective is the default. If you use the Eclipse plugin, another perspective may be open instead. You can select the Sigasi perspective by clicking the button next the perspective icon. A window pops up in which you can select the perspective.
You can right-click the perspective button to customize toolbar contents, to reset the perspective to its default layout or to save your own, customized perspective.
Quick Access
The Sigasi Studio toolbar contains a widget called Quick Access. This widget allows you to quickly find open editors, available perspectives, views, preferences, wizards, commands, etc. Simply start typing the name of the item you wish to invoke.
This page documents the Views added to VS Code by the Sigasi extension.
Project View
The Project View offers a file browser for your projects in which external folders that are not physically part of your project can exist.
This can be useful for including external IP in your projects.
The project view also offers a lot of custom Sigasi functionality e.g. library mapping, version setting, preference view, …
Linked Libraries
Any (external) libraries and files, that are not within the folder of the opened project, can be added using the Project View.
In the Project View, right-click any file or folder and select the New Linked File… or New Linked Folder… option to add files and folders from outside the project location.
The configuration of the external files and folders will be kept in the .project file in the project root.
External files and folders can be added anywhere in the project.
If you add a large folder (e.g. the unisim primitives), make sure to exclude the folder (Right-click > Set Library > Exclude from Build) from being build and only include the required files.
Or just put the library files in a folder called Common Libraries.
Then they will only be indexed and not analyzed for errors.
Buttons in the Project View
These buttons are available in the Project View.
Create a new file
Create a new folder
Refresh the Project View
Toggle linking the Project View with the editor
Collapse all folders in the Project View
Hierarchy View
Initially, the Hierarchy View will be empty.
To use the Hierarchy View, right-click an entity, architecture, or module name in the editor and select Set as Top Level from the pop-up menu.
This will populate the Hierarchy View with the structure of the top level.
As you make changes to the design, the Hierarchy View will not automatically refresh.
To refresh the Hierarchy View, use the refresh button (
).
If you want the selection in the Hierarchy View to follow your position in the editor, make sure to enable the link with editor button (
).
Buttons in the Hierarchy View
These buttons are available in the Hierarchy View.
Expand the full hierarchy
Toggle link with the editor
Toggle showing only instantiations
Refresh the Hierarchy View
Collapse the hierarchy
Preferences View
To open the Preferences View, right-click the resource you want to configure in the Project View.
This View allows to configure all preferences for your entire project, a folder, or a file.
You can change the severity of linting rules for your project.
You can modify conditional variables for VHDL 2019 projects.
You can configure include paths and initial defines for the SystemVerilog Preprocessor.
Make sure to click the APPLY button at the top right after making your changes.
Changes you make here will be stored in the .settings/ folder within your project.
This way, if you commit the settings with your project, they will be available for your fellow team members, also if they are using Sigasi Studio for Eclipse.
It is possible to run the User Interface of Visual Studio Code on one machine and do the actual development on another machine.
For example, you can be working on a Windows laptop at home, while the code lives on a Linux server in a datacenter at work.
On the laptop, you only need to install Visual Studio Code and the Remote SSH plugin.
The plugin connects with the remote server using SSH, and handles any setup required on the server.
The Sigasi extension only needs to be installed on the remote server.
Your code is kept on the server, there is no need to have a copy on the laptop. Documentation is available on the Visual Studio website.
Navigate to extensions (Ctrl+Shift+X or the icon on the left) and install the Remote - SSH extension.
From the Command Palette (Ctrl+Shift+P), select Remote-SSH: Connect Current Window to Host…. If you have an SSH config file, you can use an existing configuration here. Otherwise, select Add New SSH host and add the command to connect to your server. Note that you need to enter the full command line and not just the name of the server. Typically, the full command will look like ssh username@my.compa.ny .
To automate this, we recommend to use an SSH key-pair in combination with the SSH config file.
Once the connection is configured, connect to the server. In the bottom left corner of your VS Code window, you’ll find an indication of the remote connection.
In the connected VS Code window, navigate to plugins and install the Sigasi plugin on the remote server.
Navigate to the Explorer (e.g. Ctrl+Shift+E) and either open an existing workspace folder or clone a repository.
Check your Sigasi license setting. From the Command Palette (Ctrl+Shift+P), select Preferences: Open Settings (UI), and look for Sigasi: Path To License. With remote development, this is the license path on the server.
Note that the Sigasi VS Code extension with default settings will attempt to download a compatible Java runtime (JRE). If you want to use a JRE already installed on the server, look for Sigasi > Java: Path in the settings and enter he path to your java (11 or higher) executable. This is useful e.g. if the server doesn’t have internet access.
Now open a VHDL, Verilog or SystemVerilog file on the remote server.
Remote development license needs
When using the Sigasi extension in combination with the Remote SSH extension, the Sigasi license should be available on the remote host.
If you’re also using the sigasi extension locally, the license settings might be different for local and remote development. In that case, make sure to use the proper settings, depending on whether you’re developing locally or remote.
The settings from the User level will act as the default and can be overridden for each remote by setting the Remote [<remote name>].
When you open a project in Sigasi Studio, a number of views are presented
in the user interface. Here is a typical screenshot, with the views
highlighted.
The views provide alternative ways to access the information in a
project. They permit efficient navigation, inspection, and editing.
This chapter lists and explains the most important views of Sigasi Studio. Some views are not covered here, more specifically some views that are either inherited from Eclipse, or views that are provided by third-party plugins. Please refer to the Eclipse documentation or the specific plugin documentation for further information on those views.
Via Window > Show View. If the view is not in the visible list, choose Other… and select the view in the selection dialog.
By right-clicking in the editor and selecting Show in > ….
Some views also support opening the current selection (e.g. the Block Diagram View). This selects the element in the view that corresponds to the current selection in the editor.
Project Explorer View
This view shows the directory structure of all files in all projects.
You can use it to navigate to a particular file in your project and
select it. When you double-click on a file, the file opens in the Editor
view. If you right-click a file, you see the context menu which offers
extra commands.
You can customize the behavior of the Project Explorer View in ways
that can be particularly handy for large projects. For example, if you
click the Link with Editor icon
, the Project Explorer
will be linked to the Editor view. Now, the active file in the editor
view will always be selected in the Project Explorer.
You can apply filters to choose which files are shown. Select the icon
View Menu and then
Customize view. You can then select a filter whose matching files
will be hidden in the view. For example, you can filter out all non-VHDL
or non-Verilog files.
The Project Explorer View provides textual and graphical Label Decorations which can be controlled
in Window > Preferences > General > Appearance > Label Decorations.
Label decorators are a visual guide on the state of projects, folders, and files.
Decorators can depend on various plugins.
The following descriptions apply to Sigasi-specific decorators.
Sigasi Studio adds text decorators to the right to indicate which library a project, file, or folder is mapped in. The library name is denoted in square brackets.
If a project is in a different folder than the workspace, this is denoted within round brackets.
Other text decorators to the right of a project are probably from the Git plugin. The repository name and branch are denoted with square brackets.
Open HDL projects have a bridge-like overlay in the top right corner of the project icon.
File icons with a ‘V’ in them are VHDL or SystemVerilog source files.
Folder icons with an overlay in the lower right corner are virtual folders (white square) or linked folders (square with arrow).
Other overlays in the lower right corner are probably from the Git plugin. They indicate tracked files/folders (yellow cylinder) and non-tracked files/folders (question mark). Changed files are noted with a > mark next to the icon.
Overlays in the lower left corner are generally indicating status from Sigasi Studio: errors in files/folders are indicated with a red square and white cross while files/folders with warnings are marked with a yellow triangle with black exclamation mark .
If you exclude a file from build in Sigasi studio, the icon will be overlayed with a red forbidden entry icon in the upper left corner.
Editor View
The Editor View shows the content of files and allows you to edit
files. It is a tabbed view so that multiple files can be opened for
editing simultaneously. The currently selected file is the active file.
The Outline View displays the contents of the active file, in terms of
the HDL objects that it contains.
You can sort the elements in the outline alphabetically, by enabling the
sort button .
You can also filter all concurrent signal assignments from the outline
by enabling the Hide Signal Assignments button
.
Double-click in the Outline View to navigate to the corresponding
location in the editor.
If you enable the Link with Editor icon
and you click an
element in the Outline View, the corresponding code will be selected in
the editor.
Quick Outline View
You can also press Ctrl+O to open the quick outline.
This is just the outline view in a popup, but it also allows you to filter the shown elements.
This way, the quick outline can be used as a semanticCtrl+F, making it very easy to find a declaration in your open editor.
Pressing Ctrl+O again, when the quick outline is open, will also show the inherited members between the members of the current file.
Hierarchy View
The Hierarchy View shows the design hierarchy starting at a selected top level object. To choose a top level, open a file and right-click on an architecture (or entity or configuration or module). Then click Set as Top Level. Alternatively, you can click the Set Top button in the Hierarchy View to open a hierarchy top level selection dialog. You can use the filter field to quickly search for a certain top level.
The Hierarchy View automatically refreshes itself when you save your design files. If you have a really large design this could slow you down. You can turn the automatic refresh on and off by toggling the refresh button .
To highlight the current selection of the HDL editor in the Hierarchy View, enable the Link with Editor button . If the editor selection is part of the evaluated hierarchy tree, the corresponding hierarchy tree node will be selected.
The Hierarchy View also shows the generic and constants values of VHDL components in the hierarchy.
The internal compiler computes the generics and constants, even if they are passed down through the hierarchy, and even if arithmetic operations are used to define new values. If the value cannot be computed for some reason, the
Hierarchy View will report the value to be unknown.
When you double-click an object in the hierarchy, the Editor view is updated accordingly, possibly by displaying the contents of a different file.
Use the instantiations filter to hide everything except instantiations and structural statements.
You can launch a simulation with the button if you first set up a Launch simulator.
The Hierarchy View also offers an action Select required files, which selects all design files that are part of the current hierarchy, in the project explorer. This allows you to easily perform the same action on all files in the hierarchy. E.g. team commands, …
You can also export a CSV file with all dependencies of the selected element via the context menu: right-click and select Export Dependencies to CSV file.
Problems View
The Problems View shows problems (errors and warnings) related to your
code. These problems were reported either by the internal compiler or by
an external compiler tool.
You can navigate to the source of the problem by double-clicking on a
given problem. Problems can be sorted by clicking the column headers.
The content of this view can be customized via the View Menu . Possible customizations are
scope (workspace, project, selection), type, maximum number of
problems, …
Libraries View
The Libraries View shows the library mapping as well as the description style of the design units in all
projects. You can use it to navigate to a particular design unit in your
project. When you double-click on a file, the file opens in the Editor
view. If you right-click a file, you see the context menu which offers
extra commands for setting libraries and for setting the top level.
If you enable the Link with Editor button
, the Library View will
be linked to the Editor View. Now, the active file in the Editor View will
always be selected in the Library View.
Tasks View
It is common practice to add TODO and FIXME comments in your
code. Sigasi Studio automatically scans your comments for TODO and FIXME tags
and clearly highlights these comments with Task Tags. You can get a
nice overview of all task markers in your workspace in the Task View
(Window > Show View > Tasks).
You can configure extra tags in the Task Tag preference page:
Preferences > Sigasi > [Verilog/SystemVerilog | VHDL] > Task Tags
Bookmarks View
You can easily add bookmarks by right-clicking the line number where you want to add a bookmark.
You can get an overview of all bookmarks in the Bookmarks View
(Window > Show View > Others…).
The Bookmarks View can be used to delete bookmarks or navigate to the editor and other views.
The Block Diagram View displays a graphical (block diagram) view
of all architectures, modules, and their instantiations in your current VHDL or SystemVerilog editor.
VHDL processes are also shown in the block diagram.
This viewer automatically updates while you are editing your code and
gives a convenient way to visually inspect and navigate your code, even
when your code is still unfinished or broken.
You can open the Block Diagram View by right-clicking in the editor and
selecting Show In > Block Diagram. Alternatively, you can open the
view via Window > Show View > Other… > Sigasi > Block Diagram.
You can also double-click blocks, ports, or wires to navigate
to the corresponding HDL code. If you want to go into a block, you
have to select it, right-click and click Open Entity Declaration, Open Architecture, or Open Module.
To find an object in the Block Diagram, you can navigate from your code to the Block Diagram.
In your code, right-click a signal, port, process, or instantiation and select Show In > Block Diagram - just like when opening the Block Diagram View the first time.
If the Block Diagram already is open, the corresponding element is highlighted and the Block Diagram View is centered on it.
You can export the Block Diagram View to an image with the save
button. Both SVG and PNG are supported. Choose a *.svg filename for SVG export or a *.png filename for PNG export.
You can also export allblock diagrams of an entire project at once: Click Project > Export… > Sigasi > Block Diagrams export and select your project. All SVGs will be created in diagrams/blockdiagrams/ in your project.
The State Machine View displays a graphical (bubble diagram) view of all state machines in your current VHDL or SystemVerilog editor. This viewer automatically updates while you are editing your code and gives a convenient way to visually inspect and navigate your code, even when your code is still unfinished or broken.
You can open the State Machine View by right-clicking in the editor and selecting Show In > State Machines. Alternatively, you can open the view via Window > Show View > Other… > Sigasi > State Machines.
If you have documented your state transitions (i.e. the assignments), the comments will be added as text to the transitions in the view.
You can also double-click nodes or transitions to navigate to the corresponding HDL code.
With the button, you can toggle the display of comments on edge labels.
With the button, you can toggle the display of comments on edge labels. These labels show the code comments of the transition statements.
You also have to option to Zoom In, Zoom Out, or Zoom to Fit.
You can export state machines to an image with the save button. Both SVG and PNG are supported. Choose a *.svg filename for SVG export or a *.png filename for PNG export.
You can also export allstate machines of an entire project at once: Click Project > Export… > Sigasi > State Machine Diagrams export and select your project. All SVGs will be created in diagrams/statemachines/ in your project.
The Dependencies View visualizes the dependencies of your VHDL, SystemVerilog, or mixed language projects.
This view shows the relationships between your source files and makes it easy to see top levels and important packages.
The Dependencies View also makes it easy to detect orphaned files.
The view is automatically updated each time you save your files.
The Dependencies View has the following options:
show dependencies of the entire project. Uncheck to focus on the dependencies of the active editor only.
Group design files per library
Show design units inside design files. The design units are prefixed with an abbreviation of their kind (architecture, module, package, …" >}}
The Dependencies View can help you navigate too. Double-click a file name in the diagram to open the corresponding editor.
The Dependencies View can also be pinned. This prevents the diagram from changing when you switch editors.
You can export this diagram for documentation by clicking the save icon.
Documentation View
The Documentation View gives you a live preview of the automatic documentation Sigasi Studio can generate for your project.
With Net Search, you can find loads and drivers of a net.
A net is defined as a signal or port and all other signals and ports
that are directly connected to it. The loads are where you read the
value of the net and the drivers are where you write to this net.
To find the entire net of a signal or port, place your cursor on the
identifier and right-click. Now select Find Net. Alternatively, you
can press CTRL+SHIFT+H.
The Net Search View will appear. For big designs, it might take a
while before the results appear.
From the Net Search View, you can navigate to the VHDL code by
double-clicking the search results.
In the Preprocessor View, you can preview the expanded text of Verilog macros. This view automatically synchronizes with the active editor.
When you select text in the (System)Verilog editor, the expanded text will be highlighted in the Preprocessor View. This also works the other way: when you select text in the Preprocessor View, the corresponding, original source will be selected in the editor.
The Class Hierarchy View displays more information about the hierarchy of a class. It consists of a hierarchy tree
and a list of the class members. To open the Class Hierarchy of a class, click the class name, right-click and select Open Class in Hierarchy (or press F4).
Class Hierarchy Tree
The class hierarchy tree displays either the superclasses, subclasses, or both.
Command
Description
Class Hierarchy
Displays all superclasses and subclasses.
Superclass Hierarchy
Displays all superclasses and implemented interface classes.
Subclass Hierarchy
Displays all subclasses that extend or implement the selected (interface) class.
Show Qualified Class Names
Shows the qualified name next to each class.
Member List
The member list shows all members of the class that is currently selected in the class hierarchy tree.
Command
Description
Show Inherited Members
Shows or hides all members inherited from superclasses.
Sort By Defining Class
Sorts members by the class in which they are defined.
Hide Fields
Hides all fields in the members list.
Console View
When Sigasi Studio launches external tools (e.g. external compiler, documentation generation,…) the output is logged to the Console View.
This is a generic Eclipse view.
Different tools can open different consoles. You can switch between different consoles by clicking the -icon.
Minimap View
The Minimap View can be opened via Window > Show View > Other… and selecting General > Minimap.
This is a generic Eclipse view.
This view is another way to help navigation through large files.
It shows an overview of the entire active editor in a dedicated pane.
The part that is visible in the editor is highlighted.
The highlighted part of the Minimap View can be clicked and dragged to scroll through the Editor View.
The Editor shows the content of files and allows you to edit
files. It is a tabbed view such that multiple files can be opened simultaneously.
The currently selected file is the active file.
VHDL and SystemVerilog Editor
The VHDL and SystemVerilog (or Verilog) editors are optimized to help
you browse and edit VHDL and SystemVerilog code.
Most browsing and editing features are similar for both languages.
Sigasi Studio colors your code to make the structure more
clear. Unlike other tools, Sigasi Studio offers coloring based on the
meaning of a word, rather than just the syntax.
Sigasi Studio supports both syntax highlighting and semantic
highlighting. Syntax highlighting colors pieces of code according to
the lexical class the code belongs to, such as a keyword or string.
Semantic highlighting colors code according to its meaning.
For example, a constant is shown in another color than a signal.
Code highlighting is fully configurable for a number of
VHDL and Verilog and
SystemVerilog syntax and semantic elements.
Also, Color, background, style, and font can be
customized. Learn more about configuring
colors.
Rather than configuring every color yourself, you might want to have a
look at the supported Light and Dark themes. To switch between
themes, go to Window > Preferences > General > Appearance where
you can choose a theme. While it is possible to install additional
themes, only the Light and Dark themes are supported by Sigasi.
Type-time Syntax Error Reporting
Sigasi Studio marks VHDL and SystemVerilog syntax errors while you type. It will also report broken SystemVerilog preprocessor code.
Project Exploration and Navigation
Sigasi Studio offers powerful techniques to explore a file or project and navigate through it. This section covers: hovering, Occurrence Highlighting, Open Declaration, and Find References.
Occurrence Highlighting
If you click on an identifier, it is highlighted. In addition, all other occurrences of the identifier that refer to the same object are highlighted. Note that this occurrence highlighting is intelligent: it is not based on the identifier’s string value, but on the object that the identifier refers to.
You can turn occurrence highlighting on or off. Click the “Toggle Mark Occurrences” icon in the toolbar.
Find References
To look for occurrences of a given identifier in different files, place your cursor on the identifier and right-click. Now select Search References.
A search window will appear on the bottom of your workbench, displaying all occurrences of the selected identifier. You can easily navigate through all occurrences by clicking the Show Next Match arrow
and the Show Previous Match arrow in the search result view. Note that all occurrences are highlighted and marked with a small arrow at the left border of the editor for easy recognition.
Open Declaration and Hyperlinks
Open Declaration You can easily navigate to the declaration of any
port, signal, entity, etc. Place the cursor on the identifier,
right-click, and select Open Declaration. The editor immediately
switches to the line that declares the object. Since this operation is
so commonly used, it is assigned to the shortcut key F3.
Hyperlinks You can also navigate your code like a web browser by
clicking hyperlinks. If you press and hold the Ctrl key, hyperlinks will appear in your editor. If you click the link (while holding the Ctrl key), you will navigate to the target of the link.
Sigasi Studio offers the following links:
Link to Declaration: this has the same behavior as Open Declaration (F3)
Link to Matching Entity [VHDL]: this links a component declaration of an instantiation to the matching entity declaration. This also works for component generics and ports (Shift+F3)
Link to Matching Module [MIXED]: this links a component declaration of an instantiation to the matching Verilog module declaration. This also works for component generics and ports (Shift+F3). Modules that are instantiated as entity instantiations are also supported (label : entity work.verilogmodule port map (...);)
Link to Matching Architecture for entity declarations [VHDL]
Link to Matching When Clause [VHDL]: in finite state machines (FSMs) you can jump directly to the matching when part of your case statement from state transitions (Shift+F3)
Link to Open Declaration in Package Body [VHDL]: in packages you can jump directly to the matching declaration in the package body (Shift+F3). This also works in the opposite direction, Open Declaration in Package Body
Link to Open Declaration in Protected Type Body [VHDL]: in protected types you can jump directly to the matching declaration in the protected type body. This also works in the opposite direction, Open Declaration in Protected Type
Link to Include files in SystemVerilog sources (F3)
Link to Macro definition in SystemVerilog sources
URLs in comments
Hover
To learn more about the declaration of a given identifier, hold your mouse pointer over it.
After a short time, a popup shows you the name and datatype of the signal. This technique is called hovering.
The hover pop-up can show different kinds of information:
datatype
comments: inline documentation written at the declaration (association rules)
value: the value of constants
errors or warnings: a message, if the given identifier has an error or warning associated with it
binary/decimal conversion: for hexadecimal, octal, or binary values, the decimal equivalent
Since Sigasi Studio 4.1 the hovers also offer extra links that make it easy to navigate to the declaration, find references …
Autocomplete and Content Assist
Sigasi Studio provides powerful autocompletion capabilities. This means
that the tool can help you to complete identifiers and constructs as you are working on the code. Like other tools, the tool provides
autocompletion based on the HDL language. However, it goes much
further. It also provides autocompletion based on the design context. It can provide this additional level of intelligence as it knows all
objects that have been declared in the design.
Autocompletion Interface
Autocompletion may come from different sources, as will be discussed in the following sections. However, the user interface to initiate them is always the same. At any point, as you are entering code, you can press Ctrl+Space and the tool will suggest appropriate autocompletion.
Based on the Design Context
Sigasi Studio uses its knowledge of the design to provide intelligent
autocompletion that boosts your productivity tremendously.
The tool knows which objects are appropriate and which identifiers are
visible at any given point in the code. As you start typing and ask for
autocompletion, it will suggest the appropriate identifiers as
autocompletion candidates.
Sigasi Studio provides help to autocomplete:
component declarations
component instantiations
entity instantiations
module instantiations
case statements (based on variables/signals with an enumeration type)
SystemVerilog include paths ( `include "): triggering autocomplete between the double quotes will present a list of files and folders. If you select a folder, trigger autocomplete again to get completions in this folder.
Based on Templates
Sigasi Studio can help you to declare VHDL and SystemVerilog objects, using autocompletion based on templates.
Sigasi Studio comes preconfigured with templates for all common declarations and statements, including (for VHDL):
function, procedure
process
type: enum, file, range, array, record
signal, constant, variable
component
entity
architecture
entity/architecture pair
package/package body pair
and much more
Some autocompletions are templates that require further user input.
In such a case, the editor goes into a special template editing mode after the autocompletion has been performed.
You can use TAB to cycle through the items that have to be modified or completed.
When done, you can press ENTER to return to the normal editing mode.
The cursor will be placed at an appropriate position to continue working.
You can also configure your own templates.
To edit or create templates, go to Window > Preferences > Sigasi > VHDL or Verilog/SystemVerilog > Templates.
Here you get an overview of existing templates.
You can create New… templates, Edit… existing templates, or remove templates.
In the template editor, you can type ${ and press Ctrl+Space to see a list of the available variables.
Templates can be exported and imported. This is useful for sharing templates with colleagues.
Instantiating a Design Unit
Note: In other tools, this feature may be known as paste as instantiation or port translation.
Sigasi Studio knows all design units (entities, components, and modules) in the design and their port and parameter or generic interface, and can therefore automate much of the instantiation process. At the point in the code where you normally enter the design unit’s name, you can use autocompletion instead to suggest a list of possible design units. Upon selection, the tool will complete the instantiation with a generic or parameter list, and a port list with named associations. As an initial suggestion, each actual parameter will have the same name as its formal parameter. Of course, the actual parameter names need to be reviewed and edited by the user. Therefore, the editor will go into template editing mode after the autocompletion.
Note that design units will only be shown if they are visible in the current scope.
Automated consistent code formatting makes code more readable and helps developers understand code, whether working on their own code or when cooperating with colleagues.
You can set preferences for tabs or spaces under Window > Preferences > General > Editors > Text Editors.
Here you can set the tab width in spaces and configure to Insert Spaces for Tabs.
Whenever a tab is pressed, the corresponding number of spaces will be inserted instead.
You can also opt to Remove multiple spaces on backspace/delete so that removing leading spaces follows the indentation levels.
Format Code on Save
You can configure Sigasi Studio to automatically format your (System)Verilog and VHDL files when you save your source files via Window > Preferences > Sigasi > [VHDL | Verilog/SystemVerilog], next check Enable code format on save.
You can format (System)Verilog and VHDL files without opening them in the editor.
You can format an entire project. Right-click the project in the Project Explorer and select Source > Format.
Note that only files that are part of the build will be formatted.
You can format a selection of files. Select multiple files and/or folders in the Project Explorer and select Source > Format.
Any selected file, part of the build or not, will be formatted.
Any combination of resources can be formatted this way: multiple projects at a time, a project and a folder …
Other Editor Features
Code Folding
If you work with large files, you might want to hide certain pieces of your code. This can be done with code folding. Certain constructs, such as if-statements or process-statements can be folded so that they use a single line in the editor view. You can do this by clicking the little "-" symbol next to the statement.
You can also enable/disable code folding and perform other actions by right-clicking in the gutter (the small column to the left of your code) and selecting Folding.
Smart Caret Positioning
Smart caret positioning allows you to easily jump between words within identifiers, no matter whether you use camelCase or snake_case, by using Ctrl+Left arrow and Ctrl+Right arrow.
Sigasi Studio 4.15 added the option to disable smart caret positioning in identifiers, both in VHDL and (System)Verilog.
To change the setting, go to Window > Preferences > Verilog/SystemVerilog or Window > Preferences > VHDL where you can alter the selection of Smart caret positioning in identifiers.
Rename Refactoring
Right-click on any identifier (VHDL or SystemVerilog) and select Refactor > Rename element (Alt+Shift+R) to change the name of the declaration and all its references.
If you press Alt+Shift+R twice, you can preview the rename before applying it.
Full-screen View
Double-click on the editor tab to make it full-screen. You can also use Ctrl+M to achieve the same.
Block Selection
Note: In other tools, this feature may be known as column editing
or column select.
Block selection is an alternative to standard (paragraph) selection.
Block selection mode differs from standard selection mode in that it
allows to select rectangular regions, or to set the cursor over multiple
lines. Block selection is ideal for selecting vertical regions, for
example, a column of a table or all port names in a port map.
To toggle between normal and block selection modes use Alt+Shift+A
or press the Toggle Block Selection icon in the toolbar.
Structured Selection
Structured Select enables you to select VHDL or SystemVerilog code, based on its syntactic structure.
Shift+Alt+Up, expands the selection to the smallest syntax element that contains the current selection. You can then further expand the selection by invoking the action again.
Shift+Alt+Down, contracts the current selection to the nested syntax expression that still contains the current cursor position. You can then further contract the selection by invoking the action again.
Shift+Alt+Left, adds the syntax element left of the current selection to the selection. You can then further expand the selection by invoking the action again. You can also expand the selection in the other direction with Shift+Alt+Right
Add Parentheses or Create a String
When you select a region and press ( or [, the selected region is enclosed with the matching closing parentheses, ) or ].
When you select some text and press ", the selected text will be transformed into a string.
This works for both regular and multi-line strings.
This behavior can be disabled by unchecking Enclose selected region when typing parentheses or quotes in Window > Preferences > Sigasi > VHDL.
Show Whitespace
You can turn show or hide whitespace markers by clicking the Show Whitespace Characters icon in the toolbar.
Move and Duplicate Lines
You can easily move lines up and down by pressing: Alt+Up and
Alt+Down.
You can duplicate your current line, or the lines of the current
selection by pressing: Ctrl+Alt+Down.
The action to remove trailing whitespace is hidden by default. You can access it by pressing Ctrl+3, typing RTW, and then selecting the correct action. Alternatively, you can bind this action to Keyboard Shortcuts of your preference.
This action is being executed on the saved file, not in the editor. So before using this action, you have to make sure your file is saved.
Customize Color Preferences
There are several ways to customize color preferences in Sigasi Studio.
Choose the Eclipse Theme in the Window > Preferences > General > Appearance preferences menu.
Edit Eclipse Colors and Fonts setting in the Colors and Fonts sub-menu.
Change color setting for different text editor features in Window > Preferences > General > Editors > Text Editors
Annotation colors can be configured in the Annotations sub-menu.
Highlighting colors for differences can be configured in the Quick Diff sub-menu.
Syntax coloring for Verilog/SystemVerilog can be changed in the Window > Preferences > Sigasi > Verilog/SystemVerilog > Syntax Coloring preferences menu.
Syntax coloring for VHDL can be changed in the Window > Preferences > Sigasi > VHDL > Syntax Coloring preferences menu.
Multiple Screen Support
You can right-click the title tab of any view and select Detach to move the view into a separate window that can be dragged to another screen.
Alternatively, you can drag a view out of the current window to create a new window from it.
Once multiple windows are available, views can be dragged between screens.
The Editor View can be split or duplicated in
independent viewports that access the same file buffer.
There are 3 ways to split the Editor View.
Horizontal Split shows 2 viewports on top of each other.
Vertical Split shows 2 viewports next to each other.
Clone to a new Editor View.
This new Editor View can be detached so that
the same file buffer can be viewed on multiple displays.
To split the editor view, go to Window > Editor and select the desired action.
There are Keyboard Shortcuts
to toggle the Horizontal Split (Ctrl+_) and the Vertical Split (Ctrl+{).
There can only be a single horizontal or vertical split within an Editor View.
Multiple Editor Views can be cloned and re-arranged to obtain a custom layout with many views on the same file buffer.
Side-by-side Diff
Previous versions (local history or version control)
Comparing two files
Opening Project Files
The default way to open files in the VHDL and SystemVerilog editor is to double-click the files in the Project Explorer. But there are more methods to open files in your projects.
Open Resource
When you press Ctrl+Shift+R the Open Resource dialog opens. In this dialog, you can type a name or pattern to open a specific file name.
Open Design Unit
When you press Ctrl+Shift+D the Open Design Unit dialog
opens. In this dialog, you can search in the list of VHDL, Verilog,
or SystemVerilog design units and rapidly open the design unit you’re
looking for.
While typing, the corresponding matching characters in the design unit
descriptions are highlighted. You might notice how the design units are
not ordered alphabetically, but instead by best match.
Hint: there’s no need to bother writing special characters and upper
case letters in the search field. Our search filter will find your
design unit without them. It looks for consecutive matches in the design
unit descriptions, prioritizing those with longer and earlier matches.
Moreover, it offers smart case search: lower case letters match both
lower case and upper case letters, but you can narrow down the search by
using upper case letters, those only match themselves.
In addition to the powerful features of an Eclipse editor, the VHDL
editor that comes with Sigasi Studio supports a number of advanced editing
features that are specifically useful for VHDL editing. These are
described in this chapter.
Code Highlighting
Highlighting Classes for VHDL:
Syntax : Comment, Keyword, Number, String, Task tag
Note: In other tools, this feature may be known as paste as
component or port translation.
If you want to use instantiation based on a component (as opposed to
direct instantiation) you need to associate an entity with a component.
Sigasi Studio can automatically declare a component for an existing entity. At
the point where you normally enter the component name, you can use
autocompletion instead to show the list of available entities. Upon
selection, the tool will automatically complete the component
declaration.
Type Conversion
In VHDL design you need to do a lot of type conversions. Sigasi Studio’s
autocomplete functionality can help you with those. Put a dot (.)
after the element you want to convert, and the autocomplete suggestions
will appear. The conversion functions have descriptions like convert type and convert to ...
Smart Indentation
When you press enter, Sigasi Studio automatically adjusts the indentation of
the current and the new line. Depending on the content of the preceding
line, Sigasi Studio will automatically increase or decrease the indentation
level. E.g. an extra indent after an if-statement and removal of an
indent for the matching else-clause.
You can enable/disable this feature via Window > Preferences >
Sigasi > VHDL by toggling the Enter adjusts indentation on current
and next line setting.
Tabs vs. spaces: This feature inserts tabs characters or spaces,
according to your preferences.
Press Ctrl+Shift+F to format your current VHDL file.
This includes:
indentation
spacing between keywords and references
vertical alignment of certain symbols like `<=``
Context-based
Sigasi Studio’s formatter is context-based and tries to respect the author’s style. So depending on your source style, the formatter might make different choices.
One example is the decision to format a conditional signal assignment on one, or multiple lines. Sigasi Studio makes this decision based on the position of the first else keyword. If you put the else keyword on the first line, the formatter will put everything on one line. If you put the else keyword on a new line, the formatter will use multiple lines for the assignment.
demo<=(others=>'0')whenenable='1'else(others=>'1')wheninput='1'-- else on new lineelse(others=>'X');
Note about broken code: If your VHDL source file contains syntactical errors, the formatter cannot always figure out appropriate formatting. For this reason, the formatter is programmed to stop applying (whitespace) changes beyond unsupported syntax errors.
Configuration
You can set your preferences for tabs or spaces under
Window > Preferences > General > Editors > Text Editors.
VHDL-specific code formatting can be configured at Window > Preferences > Sigasi > VHDL > Formatting:
Preserve newlines: this option configures the formatter to not add or remove any newlines in your code.
Vertical alignment: this option configures the formatter to vertically align consecutive declarations and statements for example on <= or :.
Lowercase/Uppercase keywords: when this option is set to UPPERCASE the formatter will convert all VHDL keywords to uppercase.
When this option is set to lowercase, the keywords will be converted to lowercase.
When this option is set to ignore, the case of keywords won’t be changed by the formatter. Note: A Sigasi Studio XL
license is required for this option.
Alignment column for trailing comments: this setting configures what column Sigasi Studio aligns trailing comments to. The default is 40, you can choose -1 to not align trailing comments.
Correct Indentation Only
Sigasi Studio can also correct the indentation of your code without making any other changes. Inside a VHDL editor, open the context menu and click Source > Correct Indentation, or hit Ctrl+I. This only changes whitespace at the start of your lines.
If you select code first, only the code in the selection will be indented.
Disable Formatting in Defined Regions
You can disable the formatter for defined regions in your VHDL source files by add off and on tags:
off tag: -- @formatter:off
Turns of the formatter until an on tag is encountered
on tag: -- @formatter:on
Reenables the formatter following an off tag
VHDL 2019 Tool Directives
Sigasi Studio 4.16 introduced VHDL 2019 tool
directives, which are a simplified version of the preprocessor found in
SystemVerilog or the C family of languages.
Tool directives allow to conditionally enable code based on tool type,
debug mode, or really any other custom variable.
You can edit the defined tool directives by right-clicking your project and then going to Properties > VHDL Conditional Variables.
Stuttering is an editing technique popularized by Emacs, that lets you
type certain things really fast. Stuttering means that you tap a certain
key twice and it expands to something more complex. For example, press
the period key . twice, and the editor will expand it to a right
arrow =>. Stuttering works like double-clicking: if you type keys
slowly, the stuttering mechanism will not be triggered.
The following stuttering keys are available:
Keys
Effect
,,
<=
..
=>
;;
:=
Stuttering can be disabled or enabled through the Enable stuttering option in the Window > Preferences > Sigasi > VHDL menu.
Verilog and SystemVerilog Specific
In addition to the powerful features of an Eclipse editor, the Verilog and SystemVerilog
editor that comes with Sigasi Studio supports a number of advanced editing
features that are specifically useful for SystemVerilog editing. These are
described in this chapter. Currently, Verilog 2005 (IEEE 1364-2005) and SystemVerilog 2017 (IEEE 1800-2017) are supported.
Code Highlighting
Highlighting Classes for Verilog and SystemVerilog:
Making a typo in the file name of an `include causes swarms of errors. To prevent this, you can just press Ctrl+Space
between the double quotes of the include directive. You’ll be presented with all the files visible from
your current include path.
Smart Indentation
When you press enter, Sigasi Studio automatically adjusts the indentation of
the current and the new line. Depending on the content of the preceding
line, Sigasi Studio will automatically increase or decrease the indentation
level. E.g. an extra indent after a module and the removal of an indent for
the matching endmodule.
You can enable/disable this feature via Window > Preferences >
Sigasi > Verilog/SystemVerilog by toggling the Enter adjusts indentation on
current and next line setting.
Tabs vs. spaces: This feature inserts tabs characters or spaces,
according to your preferences.
Press Ctrl+Shift+F to format your current Verilog or SystemVerilog file.
The default formatter implementation corrects indentation only.
Since Sigasi Studio 4.15, Sigasi ships with Verible built-in. Verible is an ambitious SystemVerilog formatter that is agnostic to macro invocations and includes and therefore produces a consistent formatting result even in heavily preprocessed code.
You can enable the Verible formatter for your installation by going to Window > Preferences > Sigasi > Verilog/SystemVerilog > Formatting.
Under Select formatter, you can choose between the default Sigasi formatter which corrects indentation, and using the Verible formatter.
Sigasi ships with a recent Verible version by default.
If you’d rather run your own Verible installation, this can be achieved in Window > Preferences > Sigasi > Verilog/SystemVerilog > Formatting > Verible.
To select your own Verible binary instead of the one that comes with Sigasi, select the Use external Verible formatter instead of bundled one: option and configure the Verible installation path: option.
This page also allows you to customize the Verible formatting rules, both for the built-in and the external Verible binaries, by pressing the Edit… button.
For maximal compatibility, you need to make sure the Eclipse setting to Insert spaces for tabs is enabled and that the Displayed tab width is matching the Verible configuration.
In the Verible configuration page, configurations are grouped in the following tabs.
Indents and Wrapping
Ports and Parameters
Types
Statements and Expressions
If you want to undo your changes, you can use the Restore Defaults button, either per tab or for the entire dialog.
After applying your configuration changes, press the OK button.
To see this in action, you can have a look at our screencast.
The Verible website and README contain more information.
Verilog Version
You can configure the Verilog version via Window > Preferences > Sigasi > Verilog/SystemVerilog
and select whether *.v files are treated as Verilog (IEEE 1364-2005) or SystemVerilog (IEEE 1800-2017). *.sv files are always treated as SystemVerilog.
Include Paths and Initial Preprocessor Definitions
The fastest way to add an include path is to run the Quick Fix on `include errors in the editor.
You can configure the include paths of your SystemVerilog projects in the Verilog Preprocessor property page.
Right-click your project and select Properties > Verilog Preprocessor.
Here you can Add and Remove include paths using the buttons on the right.
You can also move the order of the include paths using the Up and Down buttons.
The Import... and Export... buttons can be used to transfer a semicolon-separated (;) list of include paths from and to the clipboard.
In the Initial preprocessor definitions field, you can configure definitions that are set before other files in the project are processed.
This allows you to, for example, set global defines without an explicit include statement.
When you hover over a SystemVerilog preprocessor directive (e.g. include ...), Sigasi Studio shows the preprocessed text.
You can find a convenient link to open the Preprocessor View at the bottom of this hover.
Ctrl+Click on `defines (or F3) will lead you to the corresponding declaration.
Autocomplete will also offer you a list of all visible `defines.
In the Preprocessor View, you can preview the expanded version of your preprocessed SystemVerilog source files.
The Sigasi extension supports semantic highlighting, however, some VS Code themes might not support it yet.
Be sure to use the default VS Code themes if you’re missing this feature.
In a theme that supports semantic highlighting, you’ll see that e.g. port, signal, and type names have a color that is different from the language keywords.
In a theme that does not support semantic highlighting, names like those of a port, signal, or type will have the default text color.
User-Defined Code Snippets
VS Code supports user-defined code snippets as explained here. To add snippets yourself, follow the steps below.
Open the Command Palette (Ctrl+Shift+P) and type Snippets
Select Snippets: Configure User Snippets
Type vhdl or systemverilog to open the corresponding JSON file where you can add your snippet like the examples below.
VHDL Snippet Example
{// Place your snippets for VHDL here.
"package declaration":{"prefix":"package","body":["package ${1:name} is","\t$0","end package $1;"],"description":"Insert package declaration"}}
SystemVerilog Snippet Example
{// Place your snippets for Verilog and SystemVerilog here.
"always posedge clk":{"prefix":"always","body":["always @(posedge ${1:clk}) begin","\t$0","end"],"description":"Insert an always block with posedge clock"}}
Sticky Scroll
You can use the sticky scroll to navigate through your HDL code more easily. This setting can be enabled with the key editor.stickyScroll.enabled
You can call Sigasi Studio from the command line to open files. Just run
sigasi yourFile.vhd. You can also drag and drop files on the Sigasi Studio
icon to open them.
You can specify a linenumber by appending +yourLineNumber to the
command line. For example: sigasi test.vhd +10 will open test.vhd at
line 10.
You can also specify the project location with the -p <project path> parameter.
If the specified project was not open in the workspace yet, this will import
and open the project in the workspace.
Note that the VHDL file you specify on the command line has to be in an
open Sigasi project to enjoy all of Sigasi Studio’s powerful editing and
navigation features. If the file you open from the command line is not
in a Sigasi Studio project, Sigasi Studio opens the file as an external
file. This is nevertheless really handy for quick
edits.
This feature enables you to configure Sigasi Studio as default editor for other
EDA tools.
Note You could get a firewall warning when you start Sigasi Studio because
Sigasi Studio opens and listens to a port (4444 by default). This is necessary
for the communication between the running Sigasi Studio instance and the
command line executable. Configure your firewall to allow Sigasi Studio access
for opening this port. Update Since Sigasi Studio 4.17.2, the listener no longer listens to port 4444.
A random free port will be used, one per user on multi-user systems.
Eclipse Plugin
Eclipse plugin users can also use this feature but need to specify a few
more command line options. You have to type
eclipse -application com.sigasi.runner.open instead of sigasi. For
example: eclipse -application com.sigasi.runner.open test.vhd +10 will
open test.vhd at line 10.
Other command line options
You can add some extra parameters to Sigasi Studio to modify the behavior.
-help : show simple command line usage information
-data <location> : specifies the workspace location
-noSplash : do not show the splash screen at startup
-consoleLog : log all debug information in the console (in addition to the regular log file)
-refresh : force refresh of workspace
-showLocation : show workspace location in title bar
-application org.eclipse.ui.ide.workbench : use the default Eclipse workbench launcher instead of the Sigasi Studio workbench launcher.
This avoids conflicts on port 4444 when running Sigasi Studio with multiple users on the same server.
Refer to the setup page for more information.
--launcher.openFile <somepath> : open the Import Projects dialog to import a new or existing project into the workspace
-Dcom.sigasi.hdt.disableAutomaticTutorial : suppress the creation of the tutorial projects in empty workspaces.
-Dswt.chromium.path=/home/user/blub : extract the Chromium binaries in blub
External Files
You can edit VHDL files without setting up a project.
When a file that doesn’t belong to a project is opened in Sigasi Studio, this
file is called an external file and it will be opened in single file mode.
Single file mode is a limited environment in which not all Sigasi Studio
features are available. Navigation only works within a file. For that reason
missing declaration are not flagged as errors.
When I double-click a VHDL file, I want it to open with my favorite VHDL editor. Sigasi Studio, obviously.
Here is how to set this up in MacOS:
Find a VHDL file in the Finder
Right-click and select Get Info
Select Open with > Other… and find your Sigasi Studio application
Click Change All… so that all other VHDL files will also get opened with Sigasi Studio.
Repeat this procedure for *.vhd files and for *.vhdl files.
Intel Quartus
In Intel Quartus, open the preferences page in Tools > Options >
General > Preferred Text Editor.
As command-line options, you should have %f +%l -p %p. Optionally you
could add -noSplash to skip the splash dialog.
AMD/Xilinx Vivado
You can configure Sigasi Studio to be the preferred editor for AMD/Xilinx Vivado.
In AMD/Xilinx Vivado, click Tools > Settings…
Open the Tool Settings > Text Editor tab
Locate the Current Editor drop down menu and instead of ‘Vivado Text Editor (default)’ select ‘Custom Editor…’
If needed click the … button and in the pop-up dialog enter:
<path to Sigasi Studio>/sigasi.exe [file name] +[line number]
Click OK to close the dialog and OK to close the Settings window.
Extra steps on Linux
If your log file contains warnings about LD_LIBRARY_PATH being set to an incompatible value or if you get an error telling the JVM terminated, you can correct this by making sure LD_LIBRARY_PATH and (optionally) LD_PRELOAD are empty when launching Sigasi Studio.
Do this by e.g. creating a script to launch Sigasi Studio and call that script from within the Vivado Text Editor settings.
Extra steps for the Sigasi Studio plugin on Windows
If you use the Sigasi Studio Eclipse plugin on Windows, you might need to take some extra steps
before you can open files from Vivado in Sigasi Studio.
Make sure to close Eclipse before making the changes below.
In your Eclipse installation
In eclipse.ini remove these 2 lines
--launcher.defaultAction
openFile
In configuration/config.ini
replace osgi.instance.area.default=... with osgi.instance.area=@nodefault - note the removal of the .default suffix
replace eclipse.application=.... with eclipse.application=com.sigasi.runner.open
In Vivado configure the custom editor with the following setting
C:\....\eclipse.exe [file name] +[line number]
The first time you might need to pick a workspace and enable the use this as default and do not ask again option.
AMD/Xilinx ISE
To configure Sigasi Studio as default VHDL editor in AMD/Xilinx ISE:
In AMD/Xilinx ISE, Click Edit > Preferences and ISE General > Editors
Select Custom instead of ISE Text Editor
If Sigasi Studio is on your path enter sigasi.exe $1 +$2 (Windows) or sigasi $1 +$2 (Linux).
If Sigasi Studio is not on your path, use the absolute path instead. If there are spaces in this
path, you need to enclose the path in curly braces . For example:c:\\My\ Applications\sigasi\sigasi.exe $1 +$2.
If you now open any VHDL file in AMD/Xilinx ISE, Sigasi Studio will automatically open the selected file.
You can find more info on configuring AMD/Xilinx ISE to work with external editors in the AMD/Xilinx documentation.
HDL Designer
To configure Sigasi Studio as external editor in HDL Designer:
In HDL Designer, click Options > Main
Click the Text tab
Press the Setup… button in the Editor section to open the Editor Command Setup dialog.
Fill the Name, Command and Arguments sections as shown.
Click the Add button to add Sigasi Studio to the list of available editors.
Press OK to close the dialog.
Press the Setup button in the HDL Viewer section and repeat this procedure from step 4.
You now can select the Sigasi entry in the list box for the Editor and HDL Viewer sections.
From now on you can double click on a file or a line in a file - for example by selecting an architecture or an entity - and Sigasi Studio will open the file at the correct location.
In addition to syntax validation, Sigasi also checks your code for
semantic problems (Linting, or Linter checks). Some of these
problems can be automatically resolved with Quick Fixes. Both syntax
checking and linting happen at type-time: new markers appear as you are
typing your code.
Linting
Code Lint is defined as code that is strictly correct according
to the language definition, but still suspicious or problematic.
Sigasi has a built-in linter, which provides info about code lint
in the design.
In addition to code linting, Sigasi can also check that file
headers and symbol names (entities, signals, variables…) follow
certain patterns. This is discussed under naming conventions.
Marker Icons
marks an info message that can be resolved automatically with a Quick Fix.
marks an info message.
marks a warning that can be resolved automatically with a Quick Fix.
marks a warning that cannot be resolved automatically.
marks an error that can be resolved automatically with a Quick Fix.
marks an error that cannot be resolved automatically.
Configuring the Linting Rules
The Sigasi linter has reasonable defaults for the configuration
of reported lint problems. However, the severity level of certain
classes of linting rules is configurable for additional flexibility.
Furthermore, some linting rules, such as the VHDL maximum line width
rule, can be tweaked
to your preference. The configuration interface to configure linting
rules for the entire workspace is available through:
For each linting rule, you can set the severity of non-conformities
in all code or in RTL-specific code. For some linting rules, more
configuration options will appear in the sidebar. Look into the
documentation of the specific rule
for more details on their effect.
Suppressing Warnings
Specific warnings can be suppressed in your code by adding a @suppress comment (-- @suppress for VHDL and // @suppress for SystemVerilog), on the same line as the warning.
You can limit the suppression to a specific warning by putting a prefix of the warning message between quotes after @suppress. Sigasi also recommends adding a reason why the warning was suppressed by adding an extra comment after @suppress:
<line with warning> // @suppress "Warning message prefix" Reason why warning is suppressed
Since Sigasi Studio 4.2 the @suppress comment also suppresses Errors.
Since Sigasi Studio 4.3 warnings have a quickfix to automatically add the @suppress comment with a matching warning message prefix.
Export Markers
You can export markers for the entire project via the Export… menu. This feature is quite useful, if you want to focus on the markers without generating documentation.
First you have to check the box that is located next to the name of your project. You can then select the format of the file (either HTML or CSV) to be generated.
Markers Report
In the report you can see all the markers in your project. The entries in the report are layed out in six columns:
Description: shows what the marker is about
Location: shows in which file the problem is marked
Line number: line number of the marker
Type of the marker
Severity: severity that is set in the linting preferences
Note that suppressed markers are also listed in the report (see the last line in the image below).
No Linting for Common Libraries
Common Libraries are considered to be production ready libraries.
Linting is skipped for all files in the Common Libraries folder.
Naming Conventions
Sigasi can check whether all sorts of names in the design -
entities, instances, modules, signals, variables… - follow
particular patterns. This may help designers to follow their
company’s or team’s coding rules. For example, coding rules may
prescribe that signal names must have a s_ prefix, that generics
names must be written in capitals, or that variable names must use
CamelCase. A naming convention rule is empty by default, which means
that the particular rule is not checked.
In addition, Sigasi can also check for header comments of files,
design units, subprograms, etc. This could for instance be used to
check whether a copyright notice or disclaimer has been included in
the file header comment.
Workspace wide naming conventions settings are accessed via
Window > Preferences > Sigasi > Verilog/SystemVerilog > Naming Conventions for Verilog and SystemVerilog, and
At the top, you can set the severity of naming convention non-conformities.
Below, you can enter the validation patterns.
Patterns use the RE2/J regular expressions syntax.
Note that names are not validated if the corresponding validation pattern is empty.
Note that you can add two patterns per name: a valid pattern which
the name must match (a marker will appear if it does not match) and an
invalid pattern which the name cannot match (a marker will appear if
it does). You can set either or both patterns per name.
You can also configure naming conventions per project, or even per
file or folder. Documentation on how to do that is
here.
Quick Fixes
Some of the VHDL lint problems can be automatically resolved with Quick Fixes.
These problems have markers annotated with a lightbulb icon (like ).
To trigger a Quick Fix, click the problem marker or press Ctrl+1 and select the Quick Fix.
Language-specific Linting Rules
The currently available linting rules are described in detail on the following pages.
Sigasi Studio offers 2 ways of configuring the severity of linting checks.
For the entire workspace, through the Window > Preferences dialog as described above.
You can override these setting by creating a settings file for your projects.
In each project, you can override the coding rules settings. You can override rules for the entire project, for folders in the project, or for individual files.
Errors/Warnings Property Page
To configure the severity level, right click the project (or file or folder) in the Project Explorer and select Properties > VHDL Errors/Warnings or Properties > SystemVerilog Errors/Warnings.
On the top of the dialog, select Enable project specific settings to activate the rule configuration on a project base.
Enabling this setting will override any settings specified at the workspace level.
For each of the available rules, you can choose from a drop-down list or you can set all severities at once by using Ctrl-A.
Note that choosing the default setting does not inherit from the workspace settings.
It will apply the Sigasi built-in default for a linting rule.
Project settings are stored in this settings file:
Where ${path} can be <project> (literally, with brackets!) to set the severity of the entire project,
/path/to/folder to set the severity of an entire folder,
or /path/to/file.vhd to set the severity of a specific file.
The valid values for the parameters are documented on the individual linting rule pages.
They are described according to these rules:
{value1|value2} means that either value1 or value2 must be used,
e.g. true for {true|false} or bit_vector for {enumeration|bit_vector|std_logic_vector}.
${integer} means the value must be an integral number, e.g. 5.
If the number must fall within a range, it is specified in a comment.
[keyword...] means the value is any number of keywords (or other strings) separated by tab characters,
e.g.
ENTITY PACKAGE
If any of the strings must contain a tab character or a single quote, escape it using a single quote.
For example, below is a list of 2 items, the first a<Tab>tab and the second a'quote.
a' tab a''quote
${regex} means the value must be an RE2/J regular expression, e.g. 0|1.
Whitespace in keys must be escaped with a back slash (\). You can add comments
with #.
The table below lists the Verilog and SystemVerilog linting rules that can be checked automatically by Sigasi.
The availability of linting rules depends on the license requirements.
To check whether the Sigasi extension started successfully, you should navigate to Sigasi’s output view.
This can be done through the Command Palette (Ctrl+Shift+P) and select Sigasi: Open Log.
The Output View should say Language client connected from ...
The logs in the Sigasi output view contain possible errors from client and server.
If errors are present, you are advised to copy them and include them in your email to support+vscode@sigasi.com.
SLF4J Errors
The following error messages in the Output View can be safely ignored.
SLF4J: Failed to load class "org.slf4j.impl.StaticLoggerBinder".
SLF4J: Defaulting to no-operation (NOP) logger implementation
SLF4J: See http://www.slf4j.org/codes.html#StaticLoggerBinder for further details.
OutOfMemoryError: Java Heap Space
If Java runs out of memory, you will see a java.lang.OutOfMemoryError: Java heap space in the log.
To avoid this, go to the settings (Ctrl+Shift+P > Preferences: Open Settings (UI) > Sigasi).
Here you can set the Sigasi > Server: Arguments. Increase the value for Xmx to more than the default 3g.
On some occasions we might ask you to share the server logs.
Before obtaining the server logs it’s best to enable debug logging.
For more detailed logging, open the settings and change Sigasi > Server > Log: Level to debug.
The location of the server logs depends on your OS.
On Linux, the logs are below ~/.config/Code/logs
On Windows, the logs are in %AppData%\Code\logs
Then find [datetime]/window[1]/exthost/output_logging_[datetime]/[0-9]-Sigasi{Tracing}.log.
For each occurrence of [datetime], choose the most recent directory available.
We recommend to open the exthost folder using the command Developer: Open Extension Logs Folder.
Note: These logs contain file names from your project so only send them to us if you’re allowed to do so.
The table below lists the VHDL linting rules that can be checked automatically by Sigasi.
The availability of linting rules depends on the license requirements.
Sigasi Studio supports a number of ways to work with external tools such as
simulators. Different techniques offer varying degrees of flexibility
and automation.
Most people will want to set up their external compilers
so that Sigasi Studio can use them to compile and start simulations.
Another way to compile your project is to export your project to a CSV (comma separated values) list
of all the files in your project, in the correct compilation order.
Learn more about how to export your project’s file list.
The third, and more advanced way of working with compilers or simulators
is to use the standard Eclipse mechanisms of builders and external
tools.
By creating a builder,
you can arrange for an external tool to be run automatically when a
Sigasi Studio project is rebuilt. By default, this happens each time you save a
file. External Tools Configuration
allow you to call any program or script from within the Sigasi Studio GUI. You
have to write and maintain the scripts yourself, but you have complete
flexibility as to what is in the scripts.
External Compilers
If you have a simulator or lint tool installed, you can use this for two
purposes:
Save-time Compilation: Compile and
check your files each time you save. Any errors or warnings will
show up in the file, on the line number of the problrem
Launch Simulator: Start the
simulator in its own window, ready to run a simulation.
If an external compiler is enabled, you can also start a simulation from
Sigasi Studio. You can start a simulation by first selecting your top level
in the Hierarchy View. Next click the
Simulate button in the hierarchy
view to launch the simulator gui with an elaborated design ready for
simulation. Sigasi Studio opens a new console for each simulation launch. You
can terminate a simulation by clicking the Stop icon
.
When you launch a simulation, Sigasi Studio opens a new console in the Console View
You can switch between different consoles by clicking the -icon.
Configure external compiler
You can configure the external compiler settings by clicking Window >
Preferences > Sigasi > Toolchains. There is a sub-page for each
supported toolchain. Before you can enable a toolchain on the main page,
you must specify its installation path. Clicking Restore Defaults on
a Toolchain page will automatically fill in the installation path if
your toolchain is installed on a default location. After you press
Apply, you can select your toolchain on the Sigasi > Toolchains
page.
For some toolchains you can specify extra command line arguments. Note
that these preference pages support Eclipse
Variables
which allow you to more easily share settings in a team.
Environment variables are supported too.
If you want to use the $HOME environment variable, you can call this variable by typing ${env_var:HOME}.
List of toolchains
By “toolchains”, we mean any tool or set of tools that processes VHDL or
Verilog code, and that is supported by Sigasi Studio. At this time, external
compiler include simulators and lint tools, but in the future it could
also include synthesis tools.
For each toolchain Sigasi Studio can support any combination of the following:
Sigasi Studio can use an external VHDL or Verilog compiler for additional code validation. At this time, Sigasi Studio supports:
vcom / vlog / vsim style compilers. These compilers include Aldec Riviera-PRO and from Mentor Graphics ModelSim and QuestaSim.
isim compiler from AMD/Xilinx.
ncsim compiler from Cadence Incisive.
Catching bugs earlier is cheaper than catching them late. Traditionally,
the first errors are found when the hardware designer decides to run a
simulation. At this time, the simulator’s compiler tool will detect
errors and fail. At Sigasi we think that this is too late. Problems
should be detected as soon as possible.
Sigasi Studio adds two extra layers of error detection to catch problems
earlier. First, there is the type-time error detector. As soon as
the designer writes an error, it is marked in the text much like a spell
checker in a word processor. Second, as soon as you save a file,
Sigasi Studio calls the external compiler for further analysis. All errors that
the external compiler finds are marked inside your file, so that you can
find and fix them easily. Sigasi Studio intelligently controls the external
compiler incrementally and only recompiles design files that need
recompilation.
All output from external compilers is logged in Sigasi Studio’s console view
for your convenience. Paths to your design files are automatically
converted to hyperlinks to ease naviation.
The table below lists some examples of VHDL errors that are detected in
Sigasi Studio at type time, at save time and with the external compiler
integration.
Check
Type time
Save time
Save time compile
Syntax errors
yes
yes
yes
Undeclared signals
yes
yes
yes
Multiple files
no
yes
yes
Data type mismatch
no
no
yes
Multiple drivers
no
no
yes
Libraries
Libraries are fully supported. But note that Sigasi Studio does not send Common
Libraries to the external compiler for compilation. These libraries are
expected to be pre-compiled. Contact support@sigasi.com if you want to
add more libraries to this list.
If your project root contains a modelsim.ini file, Sigasi Studio will add this
file to the vcom command with -modelsimini. This allows you to
configure custom settings for Mentor’s vcom.
External Tools Configuration
Select Run > External tools > External Tools Configurations to get
started, or use the icon.
To create a new configuration, first select
Program, then click
.
Enter all necessary information to start your external tool:
Name: The name for this configuration.
Location: The location of the executable. You can browse for programs and scripts in your workspace or programs on your file system.
Working Directory: The working directory for your program.
Arguments: The arguments, if any, to your program.
You can test your tool configuration with the Run button.
The following example screenshot shows how to set up configuration to
run a simulate.sh script from within Sigasi Studio.
The following example screenshot shows how to set up a configuration to
run make clean on a Linux machine.
To run the external tool just select the configuration from the dropdown
menu on the -icon. You can rerun the
last configuration by simply clicking
.
Variables in Arguments
In the arguments field you can use variables, which are automatically expanded when the external tool is run.
This allows you to do things like adding the currently selected file in the file explorer as an argument for an external tool configuration (${resource_path}).
Sigasi Studio adds following variables and parameters for VHDL and (System)Verilog projects:
Variable Name
Description
${library:<argument>}
Get the library name of <argument>. For example, to the get the library of the currently selected resource use ${library:${resource_path}}
${sigasi_toplevel}
Get the name of the current top level: library.name
${sigasi_toplevel:short}
Get the name of the current top level without library: name
${sigasi_toplevel:project_path}
Get the path of the current top level’s project root
Creating a Builder
An external tool configuration as described in the previous section
makes it easy to run an external tool, but you still have to do so
explicitly. For some programs, such as the make utility, it makes
sense instead to do this automatically upon a change in your project.
This functionality can be accomplished by a builder. We will show how to
create a builder for a Modelsim Makefile as an example.
To create a builder, right-click your project and select Properties >
Builders.
Click New… and the builder configuration window will pop up:
You will be asked to select a configuration type:
select Program.
Next, configure the builder in a configuration window pop up window:
Name: The name of your builder, e.g. ModelSim.
Location: The location of the program, e.g. /usr/bin/make.
Working Directory: The working directory for your program. For example, click Browse Workspace… and select the root folder of your project.
Arguments: The arguments to your program, e.g. --makefile=Makefile.vsim all.
With the default settings the ModelSim Makefile will only be run during
a manual build or after a “Clean”. To make sure Sigasi Studio runs make
every time you save a change to a file, click the Build Options tab
and check the During auto builds checkbox.
After configuration, the new builder will appear in the builder list.
When you close the builder configuration dialog windows, the new builder
will automatically be run. In our example of a Modelsim Makefile,
Modelsim’s messages will appear in the console view.
For the specific case of Modelsim, warnings and error messages in the
console are made clickable. When you click a message, the corresponding
location will automatically be opened in the Editor view.
You can add as many extra builders as you want. This can be useful for
additional linting tools or code generators.
Intel Quartus integration
If you are using Intel Quartus 12.1 or higher, you can use Sigasi Studio as
preferred HDL editor.
If you use the Sigasi Studio/ Intel Quartus integration, you can
easily open VHDL files by double clicking on them in Quartus. Sigasi
Studio will be aware of the entire Quartus project, so that you can
perform project-wide searches and navigation actions in Sigasi Studio.
Furthermore, if you add or remove files in the Quartus project, these
changes are automatically applied in Sigasi Studio.
Note: If you want to set up a project independent of Intel Quartus,
please read the documentation on setting up a project.
Setting the preferred editor
While importing a Quartus Project in Sigasi Studio, you have the
possibility to configure Sigasi Studio as preferred editor
in Intel Quartus.
This offers the ability to open files in Sigasi Studio from within Quartus.
Open a Quartus Project in Sigasi Studio
After you have configured Sigasi Studio to be the preferred editor in
Quartus, you can open files by double clicking on them in Quartus.
Sigasi Studio will import entire Quartus project and your file will open
in the Sigasi Studio editor view. If you make changes to your Quartus
project (like adding or removing files), these changes are reflected in
Sigasi Studio as well.
The first time you import your project, it may take a few minutes. After
that, you can leave Sigasi Studio open and double-click other files in
Quartus to open them in the Sigasi Studio editor view.
If your Quartus Project File (.QPF file) contains a reference to a
file that does not exist, Sigasi Studio will show an icon for that file with
the broken link icon .
Quartus Preferences
The first time you import a Quartus project, Sigasi Studio will ask for the
Quartus installation location. Sigasi Studio needs this path to find the
Quartus libraries. You can change the Quartus installation
location by selecting Window > Preferences > Sigasi > Toolchains.
Add files to your Quartus project in Sigasi Studio
To add a file to your Quartus project, you can use the default New
VHDL file wizard of Sigasi Studio (File > New > VHDL File).
Note that Quartus does not automatically update its UI after you add
files to your project. In order to update the files list, you should run
a work flow action in Quartus, like starting a compilation.
AMD/Xilinx integration
Setting the preferred editor
To open the Sigasi Studio editor from AMD/Xilinx, you first have to configure Sigasi Studio as preferred editor in Vivado or ISE.
You can change the AMD/Xilinx Vivado installation location by selecting Window > Preferences > Sigasi > Toolchains > Xilinx Vivado.
Sigasi Studio needs this path to find the AMD/Xilinx Vivado libraries.
ISE
You can change the AMD/Xilinx ISE installation location by selecting Window > Preferences > Sigasi > Toolchains > Xilinx ISE.
Sigasi Studio needs this path to find the AMD/Xilinx ISE libraries and to run the ISim compiler and simulator.
Export
You can export a list of all HDL files in your project, sorted in the correct compilation order.
You can use your own simple scripts to manipulate such list and run any EDA tool, including simulators, synthesis and linter tools.
To export a comma separated value (CSV) list of files in your project, right-click your project and select Export….
In the Sigasi category, select CSV File. Then select the project you want to export.
As a result, you get a file named compilation_order.csv, which lists the HDL files in your project in a valid compile order.
This file will use relative paths, except when the file is on a different drive (on Windows).
Auto-export
You can also configure Sigasi Studio to auto-export this CSV file, every time the dependencies change.
Right click on the project you want to auto-export in the Project Explorer, and select Properties and Sigasi Auto Export.
If you do not set a fixed top level name (i.e. empty top level name in the property page), Sigasi Studio will use the current top level in the Hierarchy View as input.
Note that this only works if the top level belongs to the selected project.
This information is stored in .settings/com.sigasi.hdt.shared.ui.prefs in your project.
VUnit is an open source unit testing framework for VHDL and SystemVerilog. VUnit helps you to write tests more easily and run them frequently.
Sigasi Studio can help you manage VUnit projects and enables you to run and inspect test results straight from the IDE.
When you import a VUnit project or add VUnit support to an existing project, Sigasi Studio runs VUnit in the background and automatically adds the correct libraries - as specified by the VUnit script - to your project. It also shows error markers in the VUnit script (run.py) if anything goes wrong.
Since Sigasi Studio 4.14, the library mapping of the project is automatically updated based on the contents of the VUnit run.py script.
VUnit project setup in Sigasi Studio
Prerequisites
VUnit version 4.5.0 or higher is required.
Sigasi Studio needs to know where VUnit is installed. If you installed VUnit using pip install vunit_hdl and Python is in your path, then Sigasi Studio should find your VUnit installation.
To verify whether Sigasi Studio can find your VUnit installation, go to Window > Preferences > Sigasi > Toolchains > VUnit and check the read-only VUnit installation path field.
If your Python installation is not in the path, you can configure it here in the Python executable location field.
If you have installed VUnit in a dedicated location, you should add the VUnit location to the $PYTHONPATH and make sure the $PYTHONPATH variable is visible to Sigasi Studio.
When you’re installing VUnit in a virtualenv, make sure to launch Sigasi Studio from within the terminal after activating the virtualenv.
If you installed VUnit from the Microsoft Store, you might get an error message when trying to select the Python executable.
To use Python outside of Windows Store apps, Python needs to be installed using an installer from https://www.python.org/downloads/windows/.
You should make sure that the python run.py --version command only returns the VUnit version number. Additional output will prevent Sigasi Studio to parse the VUnit version number correctly and will result in errors.
Import VUnit Project
To import an existing VUnit project, click File > Import… > Sigasi > Import a VUnit project. Next, select the VUnit script (run.py) and the location for the Sigasi Project.
The VUnit project repository comes with a number of example projects which can be imported this way. If you first specify the Python Script Location, the Project Location will be set automatically.
Add VUnit support to an existing Sigasi project
You can also add VUnit support to an existing project: Right-click your project and select Configure > Add VUnit support. Next, select an existing run.py script or let Sigasi create an example script.
VUnit project configuration and troubleshooting
The VUnit integration in Sigasi Studio gives useful feedback in the VUnit Console View.
To open this view, first open a console (Window > Show View > Other… > General > Console) and in the Console View toolbar click the triangle () next to the Open Console icon.
Select VUnit Console to open the VUnit Console View.
Since Sigasi Studio 4.14, the library configuration from run.py is used to configure the library configuration in the Sigasi Studio project.
Note that this automatic configuration does not work with linked folders.
You need to manually assign linked folders or any files/folders in them to a library.
Path separators in the run.py file need a /, also on Windows.
SystemVerilog
For SystemVerilog projects you need to manually add the VUnit include files to your projects:
Right click your project, select New > Folder > Advanced > Link to alternate location and add VUNIT/verilog/include as location.
Use the quick-fix on the failing `include "vunit_defines.svh" to add the include folder to the include paths.
Configure options for finding and running tests
In Window > Preferences > Sigasi > Toolchains > VUnit you can add different options for finding and running tests.
The Options for finding tests will be passed to run.py when generating the json file that lists the VUnit tests.
The Options for running tests will be passed to run.py when running the VUnit tests.
Select the Set VUnit output to project root to have the VUnit output stored in the project root instead of in the temp location from where VUnit is called.
Configuring the simulator
VUnit makes use of an external simulator to run tests. ActiveHDL,
RivieraPRO, GHDL, and ModelSim/QuestaSim are all supported. By
default, VUnit will try to find one of these simulators on your system
and will use the first one found.
If you want to use a particular simulator, you can set the
VUNIT_SIMULATOR environment variable to one of activehdl,
rivierapro, ghdl, or modelsim to specify which simulator to
use. In Linux, set the environment variable prior to starting Sigasi
Studio, either in your shell initialization scripts (e.g. .bashrc or
.bash_profile for bash shell), or set the variable on the fly in
your terminal window. In Windows, open the dialog Edit environment
variables for your account to set VUNIT_SIMULATOR.
You may also need to set the PATH of the simulator to use. For this
purpose, configure the appropriate environment variable for your
simulator with the correct path: VUNIT_ACTIVEHDL_PATH,
VUNIT_RIVIERAPRO_PATH, VUNIT_GHDL_PATH, or VUNIT_MODELSIM_PATH. For example:
Finally, it is also possible to configure the simulator in run.py,
as shown below.
# Some code omitted# Select simulator before calling VUnit.from_argv !os.environ["VUNIT_SIMULATOR"]="rivierapro"# Optionally set the PATH#os.environ["VUNIT_RIVIERAPRO_PATH"] = "/path/to/simulator/bin"vu=VUnit.from_argv()# More code omitted
For more information on simulator selection, check out the VUnit
website.
Run VUnit Tests
There are multiple ways to run VUnit tests in Sigasi Studio:
Right click your project and select Run VUnit tests to run all tests in your project.
Right click one or more HDL files and select Run VUnit tests to run all tests in the selected files.
Right click in the Sigasi editor and select Run VUnit tests to run all tests in the active editor.
Right click in the VUnit test name (the string in the run function call) and select Run VUnit test to run this single test only.
Rerun the tests in the VUnit view.
Inspect VUnit Test Results
When you run VUnit tests in Sigasi Studio, the VUnit view is opened. This view presents a convenient way to inspect the test results.
You can also open the Console View to inspect the entire VUnit output.
Handling specific common libraries
In Sigasi Studio, Common Libraries may be present in a project. Some
of these are standardized and available in all tools, e.g. IEEE VHDL
libraries, or the VUnit library in case of a VUnit project. Your
project may also require vendor or company specific common
libraries. External simulators, including the simulator which runs
your VUnit tests, require a particular setup to find your library.
If, for instance, ModelSim is used, then:
common libraries need to be pre-compiled,
a customized modelsim.ini with a reference to the pre-compiled libraries is required, and
VUnit needs to be aware of the customized modelsim.ini.
The latter is achieved by setting an environment variable
VUNIT_MODELSIM_INI which points at the customized
modelsim.ini. One could set this variable from the shell (Linux) or
user variables (Windows), but that is inconvenient as all projects
will use the same modelsim.ini. A better solution is to set
VUNIT_MODELSIM_INI in the run.py script, before calling
VUnit.from_argv().
# This is run.py# code omittedos.environ['VUNIT_MODELSIM_INI']='/path/to/custom/modelsim.ini'vu=VUnit.from_argv()# code omitted
Note that VUnit may still produce warnings that the library is
missing, as shown below. These warnings are harmless. They show up
because only Sigasi Studio and the simulator are aware of the library,
while VUnit is not.
WARNING - C:\Users\Wim Meeus\workspaceSigasi\VUnit-demo\design\design_top.vhd: failed to find library 'vucommon'
Alternatively, one could define the library and its
contents in the run.py script. In that case, VUnit will be aware of
the library and the warnings won’t show, but compile times will be
longer - which is exactly what common libraries are meant to avoid.
Using an external compiler in a VUnit project
If you want to configure an external compiler in a VUnit project
(e.g. for additional syntax checking), you need to ensure that the
compiler has the VUnit library. Otherwise, the compiler will flag all
VUnit constructs in your HDL code as errors.
How to compile and enable the VUnit library for an external compiler
is explained in the libraries section of this
manual.
The Sigasi Studio documentation generator makes the documentation process easier by automatically extracting information from your HDL source files. The biggest advantage is that there is only a single source for both your design and your documentation. While this gives no guarantee for the design staying in sync with the documentation, it certainly makes it easier.
The Sigasi documentation generator has following advantages:
No special coding requirements: the plain comments in your code are extracted for the documentation, no need for special annotations. Sigasi uses the same comment association as the hover provider. So to document a port, you append a comment to a port declaration. To document an architecture, you put the comment just on top of the architecture.
All included. All documentation processing is done in Sigasi/Eclipse. So you do not need to install extra tools.
Fully hyperlinked. If you export the documentation, you get a fully hyperlinked document.
Live preview: you can see what the documentation will look like while you type your code and comments.
Export Documentation
You can export documentation for the entire project or a specific toplevel by clicking the save icon on top of the Documentation View or via the Export… menu.
When you select the entire project, the design elements will be listed in alphabetical order.
When you select a specific toplevel, design elements will be ordered in a breadth-first order from the top down.
The resulting HTML file is saved in the sigasi-doc folder in the root of your project.
The generated Block and State Machine Diagrams are saved in subfolders of the sigasi-doc folder.
Sigasi Studio 4.5 introduced exporting the documentation to HTML.
You have to choose between Linked resources and Embedded resources when exporting the documentation.
Linked resources
Creates an HTML document with linked resources.
All Block Diagrams and State Machine Diagrams are in separate files which are linked from within the HTML document.
The custom CSS file, if present in the project root, will be referenced from the HTML document.
Embedded resources
Creates an HTML document with embedded resources. The documentation is in a single file.
The Block Diagrams and State Machine Diagrams are embedded in the HTML document.
The CSS from the custom CSS file, if present in the project root, will be included in the HTML <head>.
Any errors are logged to the console view.
Customization
Sigasi Studio 4.17 introduced pagination and the introduction and problems section.
Pagination
Enabling the Split pages by elements count will paginate the output documentation. This is useful for very big designs that produce documentation 100’s of MBs large.
The summary information about the design appears on the first page and fans out to subsequent pages that will contain the documentation about individual design elements.
Problems section
Enabling Include problem information will add a Problems section containing all the project’s Errors, Errors and warnings, or Errors, warnings, and infos. On top of that, the suppressed problems can also be shown.
Introduction section
If a sigasi-doc.md file is present in the root directory of your project, Sigasi will automatically include it in the exported documentation as an introductory chapter.
As usual with our documentation, this is a MarkDown file. This allows you to easily annotate the text.
The exported documentation includes the Dependency Diagram, State Machine and Block Diagrams.
If you created custom graphics configurations for one or more of your diagrams, these will be used instead of the default diagrams.
If you have multiple graphics configurations for the same diagrams, the alphabetically first one is used.
Custom CSS
If the root of your project contains a sigasi-doc.css file, this file will be used to style the generated HTML documentation.
Note that only the generated HTML will be affected and not the Documentation View.
For example, you can give the background and titles different colors. You can also change the font for the entire document or parts of it.
Entire sections for entities, architectures and modules can be given different background colors.
Likewise the list of processes can get a different background color.
The difference in documentation with the CSS settings described above is shown in the screenshots below.
Comment Association
Comments in HDL code are used to add extra information or documentation to that code.
Sigasi Studio uses certain rules to determine which comment belongs to which code.
This is important for documentation hovers, refactoring, formatting,…
Which comment belongs to which exact code is subjective.
Sigasi Studio associates comments with HDL declarations with following rules:
If there is a declaration before a comment in the same line (trailing comment), the comment is associated with this declaration. This comment can span multiple single line comments if they are aligned.
If there is no trailing comment and there is a comment with the same indentation on the line above the declaration, the comment is associated with this declaration. This comment can span multiple lines if all comments have the same indentation.
Empty lines break comment blocks
The association rules are illustrated in the image below:
The Formatter and Structural select respect (and fix) comments according to the association rules.
Special cases
VHDL components and component instantiations: If a component (or one of its ports or generics) does not have comment itself, Sigasi Studio will use the comment of the corresponding entity. This also works for component instantiations.
Comment markup with Markdown
VHDL and SystemVerilog comments are processed with a Markdown processor. This allows to add markup (e.g. bold, code, paragraphs, hyperlinks,…) to comments. This results in nicer hovers and documentation.
In hovers the complete Markdown syntax is supported. For documentation generation following features are supported:
paragraphs (add and empty comment line to break paragraphs)
line breaks (by adding two trailing spaces)
emphasis (*emphasis*)
strong (**strong**)
lists
tables (with alignment)
external links and email addresses (<https://www.sigasi.com>, [Sigasi](https://www.sigasi.com) and <sales@sigasi.com>)
Sigasi Studio 4.6 added support for Fenced Code blocks in comments.
This enables you to add text to the documentation without Markdown rendering.
To add a comment verbatim to the documentation, surround it with with triple back ticks: ```<verbatim comment>```
The BlockDiagram- and StateMachine views are a very useful way to explore and understand HDL designs, but sometimes that just doesn’t cut it.
The diagrams can be too complex and crowded to understand a design. For this reason, the diagrams can’t always be directly used in documentation. To solve this challenge you can make use of the Graphics Configuration Language.
The Language
The Graphics Configuration Language is a plain text file containing declarations and configurations, which when interpreted, result in grouping, filtering, and coloring in the diagram.
You can see it in action in the images below:
This BlockDiagram
Turns into:
This StateMachine
Turns into:
A plain text format was chosen over buttons and menus for several reasons:
It can easily be managed with your version control system because files can easily be compared and merged.
It’s easy to debug by yourself, unlike proprietary formats or UIs.
We can support you using all of our well-known features such as autocomplete, validations, formatting,…
It’s lightweight and can be used as the basis for the UI implementation.
Getting started
To get started, choose a design with a BlockDiagram or StateMachine you want to simplify.
Create a new Graphics Configuration file by going to File > New > Other > Graphics Configuration > Graphics Configuration File.
You can also press the Sigasi button on the top right of the BlockDiagram or StateMachine view.
From there, you can declare groups and configure your diagram, check it into version control, and share it with your colleagues.
Autocomplete (Ctrl+Space) helps you write most of the code while formatting (Shift+Ctrl+F) helps you to keep your file clean.
If you’re interested in the language’s exact syntax, you can find it here.
Features
The Graphics Configuration features:
Grouping
Hiding
Reassignment hiding
Block collapsing
Coloring
Regex matching
Note that in the BlockDiagram you can group blocks and wires while in the StateMachine you can only group states.
Graphics Configuration Editor features:
Autocomplete (Ctrl+Space)
Formatting (Shift+Ctrl+F)
Quick outline (Ctrl+O)
Show in BlockDiagram/StateMachine (Alt+Shift+W)
Navigate to declaration (Ctrl+click or F3 on identifier)
Double-click on a diagram element to navigate to it in the code
Hovering to show more information
Graphics Configuration for BlockDiagrams
You can express which diagram you want to filter in the first line of the file by writing diagram fullyQualifiedName. The fully qualified name in VHDL is always library.entity.architecture. In SystemVerilog, this is work.module.
E.g. if you want to filter the diagram for the architecture RTL implementing the entity ent in the work library, you use the following line as the first line: diagram work.VME64xCore_Top.RTL.
The file is read from bottom to top. You start with the above definition of the diagram, then within that, you can hide reassignments, create groups and finally, create configurations for ports, blocks, and edges.
Hiding reassignments
When using a lot of reassignments or when you’re indexing vectors, you can get a skyscraper effect in the generated block diagrams.
By using reassignments hide you can draw through the assignment blocks making the diagram a lot simpler.
Skyscraper
Hidden reassignments
Multiple reassignments
Hidden reassignments
Grouping
After hiding the reassignments you can define groups of edges or blocks.
The syntax for a group is as follows: def Type group ID (Identifiers)
Where Type is block or wire, ID is the new name of the group and Identifiers is a comma-separated list of existing IDs (Graphics Configuration, VHDL or SystemVerilog) or a regex.
The syntax for a regex is regex"regex_pattern". This uses Java regexes, you can also find a cheat sheet here.
You can also check what the regex matches by hovering over the query.
E.g. if you want to group block2 and block3 you can add either of the following lines: group block middle regex"block[23]" group block middle (block2, block3)
Ungrouped
Grouped
The same can be done for wires by using wire instead of block.
Ports can be grouped by grouping the wires attached to the ports into a bus.
Configuration
The syntax for a configuration block is as follows: Type Identifiers { ConfigurationItem* }
Where Type is block, wire, or port.
The syntax for a ConfigurationItem is as follows: hide | collapse | color GraphicsColor | reassignments hide
You can discover which colors are available here or through the autocomplete.
E.g. we can color a block, called middle, green and hide its internals: Colored and collapsed group
Configurations are not cascading (unlike CSS).
Coloring the middle block green does not turn all its internal blocks green as well.
Note that the language can not see everything: it can not see blocks, wires, or ports that are within another block.
E.g. we can’t type block block3 { color red } as block3 is part of the block middle.
To access a block within a block, we have to nest configurations.
Nested configuration
Another use case would be to hide (unconnected) ports by using port a { hide }.
Hidden port
Note that when you hide a block or port, the edges that are connected to them will also be hidden.
It is also possible to hide reassignments in configurations, as you saw in the above skyscraper example, the reassignment in the generate block was not hidden.
You can do so as follows:
Hidden reassignment in generate
Graphics Configuration for StateMachines
StateMachines are configured in the same way as the above BlockDiagrams, except the only Type that can be used is state.
The header is also slightly different, the syntax is as follows: statemachine architecture : state_variable.
For an example, you can check out step_3_state_machines.vhd (in our VHDL Tutorial) with this filter file.
Hiding labels
Labels on state transitions can be hidden using labels hide.
You can also use labels comment or labels condition to only show comment or condition labels on the state transitions.
Since Sigasi Studio is built on Eclipse, you can install third-party Eclipse plugins.
The best place to start looking for a plugin is the Eclipse Marketplace. We list some interesting
plugins here. Since these are third-party plugins, there is no official
support from Sigasi.
Installing Plugins
Unlike most Eclipse distributions Sigasi Studio is shipped without the Eclipse Marketplace plugin and the standard Eclipse update sites.
Hence, you have to add a plugin update site to install new plugins.
Click Help > Install New Software Now click Add and fill out the update site. Press OK to confirm.
Installing
Still in the Install dialog, search for the plugin you want to install. You can browse the list of available plugins or use the filter text above the list of plugins.
Select the checkbox for the plugin and click Next
Follow the instructions for the rest of the wizard.
Revision Control Systems
Sigasi Studio supports a wide range of Revision Control
Systems (also known as
Version Control or Source Control systems). Support for revision control
is based on Eclipse plugins. This section contains a preliminary listing
of the most popular revision control systems.
GIT
Recommended plugin: EGit
This plugin is shipped with the standalone version of Sigasi Studio.
While this is not strictly speaking a version control system, Sigasi Studio has
a built-in feature that keeps a local history of your files.
Learn more.
Other Systems
Some other popular revision control systems include:
Python: You can add support for Python to Sigasi Studio by installing the PyDev Eclipse plugin.
Use https://www.pydev.org/updates as update site.
Remote Collaboration
You can use the Saros plugin to remotely collaborate on the same project with multiple people. You’ll see edits from collaborators in your own editor as they happen. To install the Saros plugin in Sigasi Studio, use https://www.saros-project.org/update-site/eclipse as update site.
Opening to a Shell
If you want a quick way to open files and folders from the Project Explorer in a terminal, EasyShell is a useful plugin.
If the user interface of Sigasi Studio is unresponsive, you can interrupt the internal compilation process by pressing the stop button in the progress view. To activate the progress view, select Window > Show View > Other… > General > Progress, or click the tiny conveyor belt icon , on the right side of the status bar.
Create performance and memory snapshots
Performace snapshot
Sigasi Studio has a built-in profiler. By default this profiler is not active.
On some occasions we’ll ask you to provide an anonymized performance snapshot from the profiler.
To obtain this snapshot, follow the steps below.
Activate the profile using Help > Sigasi > Performance > Start Async Sampling
On Windows, use Help > Sigasi > Performance > Start Sampling instead.
Perform the laggy operations in Sigasi Studio
Stop the profiler using Help > Sigasi > Performance > Stop Profiling
Memory snapshot
It may happen that, as part of a support case, we’ll ask you to
provide an anonymized memory snapshot of a running Sigasi application.
To obtain this snapshot, select Help > Sigasi > Performance >
Capture Heap . You’ll be prompted for a location and a filename to
store the memory snapshot.
Sending your snapshot to Sigasi
The snapshot you’ve obtained needs to be obfuscated to anonymize it and it needs to be uploaded.
For this a snapshot_anonymizer script is provided in the Sigasi Studio installation folder.
You can verify the obfuscation first before sending the uploading the snapshot to us.
Sigasi support will provide instructions for uploading the snapshot.
The editor displays old contents of a file
If you edit a file outside of Sigasi Studio with an external editor, Sigasi Studio will normally notice the changes and ask if you want to load the changes. If
it doesn’t, you can refresh the editor’s content by pressing F5 or by right-clicking a file or a project in the project explorer and
selecting Refresh.
No content in the editor and only a cross in the editor tab
If you see empty views in Sigasi Studio on Linux: make sure libXss or libXscrnSaver is installed.
Hover makes the editor hang for ~10s
If you experience hangs when hovering over identifiers in Sigasi Studio on Linux: make sure webkit2gtk4.0 is installed.
How much local history will be stored?
Sigasi Studio stores the history of your file so that you can compare your current version with the version you saved an hour ago.
You can define how much disk space is used for storing local history in Windows > Preferences, select General > Workspace > Local History.
For more information on local history, check out this page.
I see hundreds or thousands of errors
If you see a large number of errors, you either have very, very buggy code (not so likely) or your project is not configured correctly.
Check that all files are mapped to the correct library.
Check that all stale files are ignored. (see the section on unneeded files)
Check that all third party libraries are included.
Make sure that automatic build is enabled.
Auto Build is not Enabled
Symptoms:
When you introduce an error in a VHDL or Verilog file and save the file, an error marker shows up in the file, but not in the problems view.
Navigation (Find References, Open Declaration) behaves strangely when it involves more than one file.
Other features that involve multiple files behave incorrectly: autcomplete, refactoring, …
VHDL files contain errors, but these errors do not show up in the Problems View.
Cannot select a top level in the Hierarchy View
Cannot navigate from a name in one file to its declaration in another file.
In the Project Explorer, the name of the library (for example: [work]) is not shown next to the filename.
Cause: The project does not have VHDL support enabled
Resolution: Enable VHDL support: right-click the project > Configure > Add VHDL support
Project does not have Library Mapping Information
Symptoms:
All VHDL-files in the project are not mapped
The Project contains only one error: “This VHDL project can not be built since the library mapping information is missing”
VHDL files contain errors, but these errors do not show up in the Problems View.
In the Project Explorer, the name of the library (for example: [work]) is not shown next to the filename.
Cause: The project does not have a (valid) VHDL library mapping information file
Resolution: Reset the library mapping: right-click the project > Library Mapping > Reset Library Mapping
Project does not have Common Libraries
Symptoms:
Project has many errors, in practically all files. Project build may be slow.
The standard data types (like integer and std_logic) are not recognized.
The IEEE and STD libraries are not recognized.
The IEEE and STD files are either missing or are mapped to the wrong library (for example: [work]).
Cause: Common libraries are not configured correctly.
Resolution: Reset the common libraries: right-click the project > Library Mapping > Reset Library Mapping
Sigasi Studio analyzes HDL files that I do not need
By default, Sigasi Studio assumes that all VHDL or Verilog files are part of the project. However, some projects may contain multiple files with older or alternative definitions of a VHDL object. We call these stale files, because they are no longer used. In such a case you will want Sigasi Studio to ignore certain files.
Ignored resources are decorated with a icon in the project explorer view.
Sigasi Studio startup fails: “Could not create the Java virtual machine”
On some computers, the standalone version of Sigasi Studio will fail to start with an error message similar to: “Could not create the Java virtual machine.” This happens especially on 32-bit Windows machines with less than 2GB of physical memory. The reason is that the Java virtual machine tries to allocate more memory than what is available.
In order to solve this, you can decrease the default heap size settings. You can do this by adding following lines to sigasi.ini or eclipse.ini in your Sigasi Studio installation folder:
-vmargs
-Xmx1000m
This sets the maximum heap size to 1000 MB (instead of the standard 3GB).
Note: Do not use eclipsec.exe, as this will ignore all of the settings configured in the eclipse.ini file.
Sigasi Studio shows a startup message about port 4444 already being in use
If you want to run Sigasi Studio on a server with multiple users, the configuration files should be updated according to the descriptions here.
I want a clean restart
If you ever suspect that the state of your project is inconsistent in Sigasi Studio, you can do one or all of the following things. Consider these
steps to be advanced usage; you should not need them during normal operation.
Force a clean compilation
You can force a completely clean compilation by selecting: Project > Clean … > Clean All Projects > OK.
Remove stale markers
Sometimes markers remain visible, even after the problem is fixed or when a file is excluded from compilation. We call these stale markers and they are can be caused by a crash during compilation.
You can delete these stale markers from the Problems View: In the Problems View, select the markers and press DEL (or right-click and select Delete).
Note that during the next build, the tool may generate new markers. If you want to suppress certain warnings, you can configure the linting rules.
Remove the cache
For faster performance Sigasi Studio is using a cache.
Sometimes the cache can get corrupted which might cause internal errors.
The cache is located in your workspace.
By default, Sigasi Studio’s workspace is located in ${HOME}/workspaceSigasi.
To remove the cache, stop Sigasi Studio and delete the folder workspaceSigasi/.metadata/.plugins/com.sigasi.hdt.shared.ui/resource.cache/sigasiBuildCache.
Remove the workspace state
Much of your configuration and cached data is stored in your workspace.
By default, Sigasi Studio’s workspace is located in ${HOME}/workspaceSigasi.
A lot of this data is stored in the hidden .metadata directory.
Sometimes, a part of your metadata can become corrupt.
It can help to remove the .metadata directory (take a backup first!).
This clears all of your workspace state.
You will need to enter your license code again.
You will need to import your projects again. Import > General > Existing Projects into Workspace
Keep getting reports about an “Incompatible version of Quartus”
If you are using the integration with Intel Quartus. Some people keep getting a dialog box that says something like:
Incompatible version of Quartus
Project interface was created with an older, incompatible version of Quartus.
Is it OK to upgrade the project to match the installed version of Quartus?
Obviously, you should upgrade the project. If this message keeps popping up, you may want to check that Sigasi Studio is using the correct version of Quartus, in the Sigasi Studio application: Window > Preferences > Sigasi > Toolchains > Intel Quartus.
Contact support
If this troubleshooting guide did not solve your problem, please send us an email
.
Any of the following information will help us help you:
Steps to reproduce your problem
Description of the expected behavior and the actual behavior.
The version number of your Sigasi Studio: Help > About Sigasi > Installation details Note that the version number contains the date of the release. (For example, version 2.0.1.20110809… was released on August 9, 2011.)
As you become more experienced with Sigasi Studio, you will find that there are a number of actions that you perform quite often. At some point, you may feel that the GUI-based approach becomes too slow for these actions. For that reason, Sigasi Studio provides a number of keyboard shortcuts. They are a great way to boost your productivity. A printable cheat sheet with all shortcuts on one page is available for download.
In this chapter, we describe the available keyboard shortcuts.
Top keyboard shortcuts
In this section, we list the most important shortcuts.
Open Resource (Shift+Ctrl+R): Shift+Ctrl+R opens a dialog that allows you to swiftly open an editor on any file in the workspace.
Open Declaration (F3):
Use F3 to navigate to the declaration of the selected identifier.
Open Design Unit (Shift+Ctrl+D): Shift+Ctrl+D opens a dialog in which you can type a name or pattern to open a specific VHDL or SystemVerilog design unit name.
Backward History (Alt+Left):
Often, when you navigate to a declaration you want to go back to where you came from; just press Alt+Left.
Content Assist (Ctrl+Space):
With content assist (autocomplete) you can really speed up coding VHDL. Just press Ctrl+Space to get a suggestion of possible autocompletes in the current context.
Go to next marker (Ctrl+.)
Does your file contain warnings or errors? Quickly navigate to the next problem by pressing Ctrl+. (Ctrl+, jumps to the previous problem).
Quick Fix (Ctrl+1):
To fix problems even quicker, navigate to the problem with the previous shortcut. Press Ctrl+1 to activate the Quick Fix, select the fix with the UP or DOWN keys and execute the Quick Fix with Enter.
Go to Line (Ctrl+L)
You can directly jump to a certain line with this shortcut. You can display the line numbers by right-clicking on on the gray bar on the left side of the editor view and clicking on Show Line Numbers.
Search references (Shift+Ctrl+G)
To search for all occurrences of a given identifier, just select the identifier and press Shift+Ctrl+G. The search view is displayed, with a match for each occurrence (possibly in multiple files)
Rename Refactoring (Shift+Alt+R)
Once you get used to the rename refactoring you will be using it all the time. Use Shift+Alt+R to run it even quicker.
Toggle Block Selection (Shift+Alt+A)
Switch between regular and block selection mode.
Structured Select (Shift+Alt+Up/Down/Left/Right)
Select VHDL or Verilog code, based on its syntactic structure. (Structured selection)
Format (Shift+Ctrl+F)
Format your current VHDL or SystemVerilog file.
Quick Access (Ctrl+3, This is the shortcut to use, when you forgot the shortcut you actually need.)
With Quick Access you can quickly find open editors, available perspectives, views, preferences, wizards, commands, etc. Simply start typing the name of the item you wish to invoke.
If you are using MacOS, most of these keyboard shortcuts use Command instead of Ctrl. To inspect the exact list of keyboard shortcuts, go to Preferences > General > Keys.
Customizing keyboard shortcuts
Keyboard shortcuts can be easily customized via Preferences > General > Keys.
This preference page also enables you to select the Emacs scheme, for more Emacs-like keyboard shortcuts, or (if you have installed the UltraEdit key bindings for Eclipse plugin) the UltraEdit key bindings.
If you’re looking for Vi or Emacs keybindings, have a look at Third Party Plugins.
The advanced setup of Sigasi Studio is meant for engineers and organizations who want to:
automate the setup of Sigasi Studio
automate the setup of a project (or a set of related projects)
combine Sigasi’s VHDL and SystemVerilog support with other programming languages, version control settings, or different Eclipse plugins
ensure that all team members share the same settings (indent style, templates, linting preferences…).
The advanced setup uses
Oomph, a highly
customizable installer for Eclipse. Oomph is configured with setup
files. Most of the team members will use these files when setting up a
new version of eclipse and/or when they join a new project. Only every
now and then, e.g. at the start of a new project, a setup file needs
to be created or updated.
For the standard setup procedure for Sigasi Studio, look here.
The user perspective: using existing setup files.
Setting up the latest version of Eclipse with the Sigasi Studio plugin
is easy and straightforward. One or two files are needed:
The product setup file determines the Eclipse setup, e.g. plugins and workspace settings.
The optional project setup file tells Eclipse how to set up a project, e.g. from a version control system.
To get the installation started, download, unzip and run the Eclipse
installer. In the top-right
corner, click the 3 horizontal bars (the burger menu) and select
Advanced Mode….
Next, click on the plus icon next to the filter text and enter the URI
of the product setup file. This can be a file on your system or a web
link, e.g. to a file on your team’s internal web page. For demo
purposes, you can use our example file:
https://insights.sigasi.com/resources/manual/SigasiStudio.setup. Click
OK to close the pop-up.
Select the desired product setup under User Products and click Next >.
Now you can optionally select a project to set up. Again, click the
plus icon next to the filter text and enter the URI of the project
setup file. You may want to try our demo project from
https://insights.sigasi.com/resources/manual/SigasiDemoProject.setup
which will set up a Sigasi project using git version control. Select
the desired project (checkbox) and click Next >.
Next, configure the path for your Eclipse installation, workspace and
project. Check Show all variables to see all relevant paths. Make
changes if required and click Next > to continue. In the next
screen, click Finish to start the setup process.
At the end of the product setup (Eclipse install), Eclipse starts
up. If a project setup was selected, a second Eclipse installer starts
for that purpose. When finished, the Eclipse installer window(s) may
be closed by clicking Finish.
Your new Eclipse with Sigasi Studio is now ready, with the optional
project if one was selected.
Setting up the setup files
So far, we’ve seen how a user can set up Eclipse, Sigasi Studio and
projects quickly and easily using setup files. These setup files are
convenient for teams to keep tool settings consistent between team
members.
This section discusses how to create and modify setup files. Setup
files use the XML format, which means that they are structured text
files and therefore human readable. The Eclipse Oomph plugin has a
convenient graphical editor for these files. Using a text editor is
error-prone and therefore not recommended.
Setting up Eclipse Oomph
Oomph is an Eclipse plugin, so you’ll want to either run Oomph in your
current Eclipse, or install a separate (minimal) Eclipse. The Eclipse
installer can be found
here. Recent versions of Eclipse
contain Oomph by default, so you shouldn’t need to install anything
extra.
If your Eclipse doesn’t contain Oomph, open Eclipse, go to Help >
Install New Software…, enter
http://download.eclipse.org/oomph/updates/release in the box next
to Work with, select the Oomph Setup > Oomph Setup and proceed
with the installation.
Then, create a new General project to contain the setup files:
File > New > Project… > General > Project, name the project and
click Finish.
Now you can either create new product and project setup files in this
project, or copy (drag & drop or otherwise) files into the project for
customization.
Product setup file
For a product setup file, it is recommended to start from one of our
examples: either a fairly minimal
SigasiStudio.setup or an
example in which a few extra workspace options are configured:
SigasiStudioPlus.setup.
Place one of these files in your Oomph project and open it for further
customization.
If you prefer to start from scratch, right-click your Oomph project
and select New > Other… > Oomph > Setup Product Model, and check
out one of the above examples for the basic configuration.
Both examples will install Eclipse with Sigasi Studio and Git revision
control. The minimal example will, in addition, configure the maximum
heap space for Eclipse, it will enable the Sigasi perspective, and it
will turn off the Preferences Recorder. The extended example, shown
above in the Oomph editor, contains further options for linting
severities, formatting options and an autocomplete template.
Note the three groups of settings:
Eclipse Ini: settings that will go in eclipse.ini.
P2 Director: plugins to install and the repositories where they
can be found. Here you can add additional plugins, e.g. to support
an additional programming language or a different revision control
system. To add an item, right-click P2 Director, and select
New Child > Requirement for an additional plugin, and
subsequently New Child > Repository for the plugin repository.
Custom preferences: workspace settings. Here you can fine-tune
workspace settings to the need of your team. To add a new
preference, first find the key and the value of the preference
which you want to configure (see below). Then, right-click Custom
preferences and select New Child > Preference. Then fill out
the key, the value and the optional description.
Finding keys and values of workspace preferences is easy as
follows. First, install a custom Eclipse with the setup file as it is,
i.e. without the preference. In that copy of Eclipse, select
Window > Preferences > Oomph > Setup Tasks > Preference Recorder, check the
Record into: checkbox and click the Open the recorder target
file icon on the same line. Then, set other preferences as
desired. After clicking Apply and Close, a pop-up like the one
below shows the information for the key and value to configure.
After adding the desired preferences and plugins, it’s time to save
the setup file and use it with the Eclipse installer, as described
here.
Project setup file
For a project setup file, it is recommended to start from our example:
SigasiDemoProject.setup,
which you can copy into your Oomph project and open for further
customization. If you prefer to start from scratch, right-click your
Oomph project and select New > Other… > Oomph > Setup Project
Model, and check out the above example for the basic configuration.
Specify the location of your project and save the file. Now it is ready
for use in the Eclipse installer.
We recommend to save project preferences in version control with
the project, rather than in a project setup file. That way, changes to
project settings get propagated to all team members effortlessly, and
each revision of the project contains matching project settings. To
that end, store .project, .library_mapping.xml and .settings of
your project in version control.
Sigasi Studio supports VHDL versions 1993, 2002, 2008, and 2019 as well as Verilog (2005) and SystemVerilog (2012).
You can select the default VHDL version to use in Window > Preferences > Sigasi > VHDL.
You can set the default Verilog/SystemVerilog version in Window > Preferences > Sigasi > Verilog/SystemVerilog.
Since Sigasi Studio 3.2, you can also set the language version
per project, folder, and file.
In the Project Explorer, right-click your project, folder, or file; select Properties > VHDL Version
or Properties > (System)Verilog Version and select the version via the dropdown menu.
When you change the language version of a file, only that file is affected.
However, when you change the version of a folder, then everything in that folder will have the new language version.
Any overrides in the folder and its sub-folders will be removed.
When you are defining the language versions for a new project you should map from top (project root) to bottom (files).
The version information is stored in <project path>/.settings/com.sigasi.hdt.vhdl.version.prefs and <project path>/.settings/com.sigasi.hdt.verilog.version.prefs.
We recommend you add this file to version control so you can share it with your team.
Notes:
VHDL libaries: Any new project that you create will have the Common Libraries (STD and IEEE) that correspond to your selected VHDL version.
Your existing project will not be modified.
If you want to update the Common Libraries for an existing project, right-click the project and select Library Mapping > Reset Common Libraries.
Since Sigasi Studio 3.3, you will get a warning if your Common Libraries do not match the VHDL version of your VHDL file.
You can use the proposed quick fix to resolve the issue.
If you want to compile VHDL 87 code, you should select the “1993” option. There are no checks to warn about constructs that were not supported in 1987, but that were introduced in 1993.
Sigasi Studio does not send the Common Libraries to an external compiler. It is expected that these libraries are pre-compiled.
Colors and Fonts
You can configure the code coloring by selecting Window > Preferences > Sigasi > VHDL > Syntax Coloring.
For each class of semantic and syntactic elements, you can select the font, letter color, background color and style (bold, italic, underline, strike through).
Font Size
Sometimes you want extra small fonts such that you can fit more content on your screen. Other times you
may want extra large fonts such that you can use a beamer and your audience can see what you are doing.
Most fonts, including the font that is used by the editors, can be controlled in the preferences:
Window > Preferences. Fonts are controlled in General > Appearance > Colors and Fonts. The font of the editors is configured in Basic > Text font.
Some fonts cannot be controlled from this preference page. These fonts are defined by general system settings and are used for displayiing the menu names, the Project Explorer View, and the Outline and Hierarchy Views. On
Windows, you can change these fonts by changing your font settings in the Windows Control Panel. On Linux, these fonts are controlled by a settings file: ${HOME}/.gtkrc-2.0. You can change the font by adding a line like:
gtk-font-name = "Sans 10"
You have to restart Sigasi Studio before these changes take effect.
Annotations Colors
Annotations are colors added on top of your text editor, and to the right of your text editor, in the scroll bar. The image below shows annotations for each occurrence of a certain data type. The color has
been changed to bright green.
You can change the color of annotations in Window > Preferences > General > Editors > Text Editors > Annotations.
For the particular case of occurrence annotations, you want to modify the color for annotation type Occurrences.
If more than one Occurrences type is displayed, you need the org.eclipse.xtext.ui.editor.defaultOccurrenceAnnotation.
The others may refer to occurrences for Java or other plug-ins.
Tabs and Spaces
If you want to use spaces instead of tabs, you can set your indentation preferences in Window > Preferences > General > Editors > Text Editors. Here you can select choose to Insert Spaces for Tabs and choose your preferred Displayed Tab Width.
The “Gutter”
The Gutter is the small area to the left of the editor view. It is used for displaying extra information about your code.
Line numbers: What line is this?
Quick Diff: Did this file change?
Folding: hiding pieces of code from view
Markers: error markers, warnings, and bookmarks.
There is not much to configure about markers, but the other categories can be turned on or off.
Line Numbers
To enable line numbers, right-click in the gutter and select Show Line Numbers.
Quick Diff
Instead of using a compare editor, you can enable quick diff support and see the changes within the text editor. This feature can be enabled via Window > Preferences > General > Editors > Text Editors > Quick Diff.
When you enable Quick Diff, you can see changes in the active editor with the version on disk (or the latest version in version control), by hovering the annotations in the gutter.
You can choose the severity of linting rules in Window > Preferences > Sigasi > VHDL > Errors/Warnings.
Read more information about Linting and Quick Fixes.
Language
Eclipse is available in several languages, and you can install the language pack of your choice. Read more in this support article: Installing translations for Eclipse
Keyboard Shortcuts
Sigasi Studio comes with a large number of Keyboard Shortcuts preconfigured. You can configure keyboard shortcuts (key bindings) in Window > Preferences > General > Keys. You can modify individual keyboard shortcuts or add new key bindings.
There is also a preconfigured scheme for Emacs-like keyboard shortcuts.
After you have configured your keyboard shortcuts, you can export your settings and share them with your colleagues (or re-import them on another computer):
To export, go to File > Export… > General > Preferences, and select Key Preferences. To import that file: File > Import… > General > Preferences.
Sigasi Studio’s license key management system is based on the well known FlexNet (a.k.a. FlexLM) license manager.
Sigasi Studio supports both node-locked and floating license keys.
The Sigasi Studio edition is controlled by the license key.
This page explains how to configure your Sigasi license in Sigasi Studio on Eclipse.
There is a separate page documenting License Server Management.
Node locked licenses
If you have a node-locked license, you can enter your license key directly in Sigasi Studio.
Open the Sigasi Studio License Key preference page: Window > Preferences > Sigasi > License Key
Click Edit License File
paste your key in the dialog
An example node-locked license looks like this. Note that the first line starts with INCREMENT
Configuring Floating license in Sigasi Studio (FlexNet Client)
In order to use a floating license, Sigasi Studio needs to know how to contact the server.
The license server can be configured in Sigasi Studio or using an environment variable.
Configure the license server in Sigasi Studio
In Sigasi Studio, navigate to the License Key preference page via:
Window > Preferences > Sigasi > License Key.
Next enter <portnumber>@<servername> in the License key path. For example:
27000@myserver.example.com
If you have redundant license servers, enter each of the license servers separated using “,”.
It is recommended to specify the primary server first in the list.
For example:
If you have multiple, non-redundant license servers, the servers should be separated using “:” on Linux and using “;” on Windows.
If you leave the License key path empty, Sigasi Studio will try to use an environment variable
to find the license server.
Configure the license server in an environment variable
You can also set your license server via an environment variable instead of configuring it in Sigasi Studio.
Both SIGASI_LM_LICENSE_FILE and LM_LICENSE_FILE are supported.
When SIGASI_LM_LICENSE_FILE is set, LM_LICENSE_FILE is ignored.
Note that if you want to use an environment variable, you can not enter a path in the License Key preference page.
The value on the License Key preference page has priority over environment variables.
You can release a floating license (check a license in) without closing your Sigasi Studio application or Eclipse application. This is useful if you use Eclipse to edit other files than VHDL files, like C or Tcl.
First, make sure that all VHDL and Verilog files are closed and all VHDL and Verilog projects are closed. Next select Help > Sigasi > Floating license > Release Sigasi Floating Licenses
To get the license back (to check the license out), open the license dialog Help > Sigasi > Configure License… and press Apply.
How to block Sigasi Studio from checking out a license?
If you have configured an environment variable with the location of a FlexNet license server, you can instruct Sigasi Studio not to check out a license by setting the Sigasi Studio License key to none.
Checking out and releasing the XPRT license
If you have a license for Sigasi Studio XPRT
, this is actually licensed as a com.sigasi.hdt.xl FlexNet feature
combined with a com.sigasi.hdt.xl.doc FlexNet feature.
The XL license is checked out as described above.
The XPRT license is checked out automatically in the following cases:
When you open the Block Diagram view
When you open the State Machine view
When you open the Class Hierarchy view
When you open the VUnit view
When you export documentation
When you click Help > Sigasi > Floating License > Check out Sigasi Studio XPRT license
The XPRT license can be released via: Help > Sigasi > Floating license > Release Sigasi Studio XPRT Floating Licenses.
Talkback is a Sigasi Studio service that automatically collects metadata about how Sigasi Studio is used and sends this metadata to Sigasi through a secured connection.
Why should I enable Talkback?
By enabling Talkback you help us improve Sigasi Studio:
Talkback lets us determine which features are heavily used. This helps in planning which kind of features are valuable for you as Sigasi Studio user, so that we can adjust our product roadmap.
Talkback collects performance statistics, that we can relate to the project sizes. Together with our in-house performance tests, this helps us keep the Sigasi Studio compiler and user interface fast.
Talkback helps us reduce software errors by collecting incident reports from a wide range of use cases.
The activation of Talkback is required to enable our free educational and open source licenses.
Talkback is automatic and less cumbersome than feedback surveys.
The end result is that you can use an always-improving Sigasi Studio.
How does Sigasi use this information
Sigasi uses the information transmitted by Talkback for marketing and product planning and development. We use it for deciding which features to develop and improve, for finding and fixing bugs and for finding and fixing performance issues.
What kind of information is sent through Talkback?
Talkback transmits meta-information about your project, operating system, Java Virtual Machine, tool usage, build performance, system statistics, license type, and incident reports (stack traces) that occur due to software errors.
Talkback never transmits any HDL code. All transmissions are through an industry standard SSL secure connection.
In the Talkback transmissions, we identify your Sigasi/Eclipse workspace using a generated identifier (a standard Java universal unique identifier UUID).
Talkback stores all the information it transmits in a local log file, so that you can inspect it. The information is human-readable, in JSON (JavaScript Object Notation) format.
You can access the Talkback log to verify by clicking Window > Preferences > Sigasi > Talkback > Talkback log.
This log file is rotated for each new Sigasi Studio session or when the log reaches a certain size.
How do I enable or disable Talkback?
Talkback is always disabled by default. To enable Talkback, or to disable it later on, do the following.
In Eclipse
Click Window > Preferences > Sigasi > Talkback and select or deselect the checkbox “Enable Talkback”.
In VS Code
Talkback in VS Code only concerns the LSP server process, the client VS Code extension instead uses the Telemetry setting.
Press Ctrl+Shift+P to open the Command Palette
Select Preferences: Open Settings (UI)
In the Setting tab, navigate to Extensions > Sigasi > Enable Talkback
Select or deselect the checkbox
Telemetry
The Sigasi Studio for VS Code will collect telemetry data when an error occurs within the extension itself. This is used to fix bugs and help guide the direction of the product. This is aligned with VS Code’s telemetry and can be tweaked using the VS Code setting: telemetry.telemetryLevel. Note that this VS Code setting is on by default.
For more information regarding telemetry refer to VS Code Telemetry.
What about my Firewall or Proxy?
Talkback uses the https protocol to send the information.
If your firewall blocks SSL connections Talkback will not be able to send diagnostics.
Your firewall should allow outgoing connections to https://talkback-sigasi.sigasi.com/.
Talkback does not support Proxies. If Talkback is unable to connect to our server directly because of your firewall or proxy server, you need to purchase a commercial license.
Features like Talkback are against our corporate policy, even if it is disabled. What can I do?
Please send us an email
so that we can discuss a solution for your company.
The main purpose of HDL languages is to describe a design that would be synthesized and implemented in hardware. However, both VHDL and Verilog also provide additional features for writing verification code to check a design by simulating its behavior. In order to do so you can write testbenches that provide stimulus to DUT inputs and assert if their outputs have unexpected values. More sophisticated language constructs can be used to do more complex checks. The problem with such verification code is that it’s not synthesizable.
You should not use this verification subset of language features in the actual design. For better synthesis Quality of Results (QoR) many other rules should also be followed. However, since these rules only apply to a synthesizable design, there’s usually no need to restrict oneself to following them in verification code.
In order to provide better feedback, Sigasi Studio detects what parts of the code are supposed to be synthesizable and verifies synthesis rules for that code. In order to do so, it detects a description style for design units. The description style can be detected as:
Testbench - top level verification module
Behavioral - additional design units that are supposed to be used for verification purposes
RTL - design units that are part of an actual design that would be synthesized
Sigasi Studio provides the possibility to specify a different severity for rules in RTL and non-RTL (testbench or behavioral) code.
It’s also possible to disable some checks for RTL or non-RTL code by setting the corresponding severity to ignore.
VHDL
In VHDL a description style is detected for every architecture. It’s possible to select how the description style is detected:
Either by detecting verification code
Or based on architecture names
By default, the detecting verification code method is used. In this case, an architecture is detected as:
Testbench, if the corresponding entity does not have any ports, otherwise
Behavioral, if it contains:
non-synthesizable processes, e.g., no sensitivity list or multiple wait statements
uses the std.textio package or declares file types
RTL, in all other cases
This mechanism provides good results in most cases. However, if more fine-grained control is required, you can choose to detect the description style based on architecture names. In this case, you have to specify name patterns that are to be matched against them. An architecture is then detected as:
RTL, if its name matches the valid pattern and does not match the invalid pattern, otherwise
Testbench, if the corresponding entity does not have any ports, or
Behavioral, in all other cases
Verilog
For now, there are no rules that would benefit from a design unit description style, so no detection of description styles is performed.
Libraries View
You can examine the description style detected by Sigasi Studio for VHDL architectures in the Libraries View:
Sigasi Studio’s license key management system is based on the well known FlexNet (a.k.a. FlexLM) license manager.
Sigasi Studio supports both node-locked and floating license keys.
The Sigasi Studio edition is controlled by the license key.
This section details the set-up of the license server when working with floating licenses.
License server setup
Download the FlexNet daemons
The version of the FlexNet daemons must be equal or higher than the FlexLM version of Sigasi Studio. The required version can be found in Sigasi Studio: Window > Preferences > Sigasi > License Key and look for the FLEXLM_VERSION line.
By default, Sigasi license files use ports 27000 and 27001 on your license server.
If these ports are already in use on the server, you can change the port numbers in the license file.
The port of the Sigasi daemon is set on the DAEMON line. For example: DAEMON sigasi port=27001, forces the Sigasi daemon to use port 27001.
The port of the FlexNet daemon is set on the SERVER line For example: SERVER your_server_name1 BD41FCF5DE27 27000, forces FlexNet to use port 27000. This is the port clients need to use to check out a license.
You can change the port numbers and your_server_name1 without breaking the signature.
If you have a firewall, remember to open these ports for access.
Starting the FlexNet and Sigasi daemon on Linux
the easiest way to start the Sigasi FlexNet daemon is like this (on Linux)
Create a folder to hold the license manager software, in this example we will use D:\Sigasi\license.
Unpack the zip file into the license folder (D:\Sigasi\license)
Run the license configuration tool lmtools.exe as administrator.
Save the license file supplied for Sigasi Studio to the license folder
Using a text editor, edit the license file and replace your_server_name1 with the name of the machine you are using, for example, from: SERVER your_server_name1 74e50bb0911e to: SERVER Maple 74e50bb0911e. Note: If you are not sure of the name of the machine you are using click on the System Settings tab of lmtools, where it is shown, see below:
Click on the Config Services tab and fill in the following, use the browse button when available:
Service Name: Sigasi License Manager
Path to lmgrd.exe: D:\sigasi\license\lmgrd.exe
Path to license file: D:\sigasi\license\sigasi.lic
Path to the debug log file: D:\sigasi\license\debug.log Note: You will probably need to type the “Path to the debug log file”, in full as the file will not exist so you cannot browse to it.
Ensure both the following check boxes are checked:
Use Services
Start Server at Power Up
Now click the Save Service button, and click yes on the confirmation dialog.
Switch to the Start/Stop/Reread tab and start the server.
The license server should now be configured correctly, and looks a bit like this one
Troubleshooting
If your license key does not work, the first things to check are:
Which version of the Sigasi license daemon are you using? Note: The Sigasi 2 daemon needs to be updated to run Sigasi 3. Otherwise you will see an License is not valid (Internal Flexlm Error) error message in the Sigasi Studio preference page.
Is the MAC address correct?
Since Sigasi Studio 4.3, on Linux Sigasi Studio uses the ip command to list MAC addresses instead of the now deprecated ifconfig command. If you’re using a version of Sigasi Studio older than 4.3 on Linux, you might need to install additional packages to obtain the ifconfig command.
On Arch, Debian or Ubuntu Linux, the “net-tools” package is needed.
On (Open)Suse the “net-tools-deprecated” package is needed.
Has the license expired?
Did you copy the license string exactly as it was sent to you?
Did you accidentally try to use a License Token as a license key?
A License Token is a 24 character string. You can use your license token to Activate Your License Key.
If your floating license server does not function properly, try the following steps:
Start the FlexLM daemon with the -z option to see what is going wrong
You can check that the FlexNet daemon is running as expected by following these steps:
Download the daemon zip file on the client machine
Run lmutil[.exe] lmdiag -c "<port>@<server>" -n
If the server is running correctly, you should see a description of the valid FlexNet features served by you license server.
Make sure the server name in the license key file is correct.
Make sure both the Sigasi and FlexNet daemon are the same version (i.e. from the same zip-file from the Sigasi download server). If you need to mix versions, the FlexNet daemon version should be equal to or higher than the Sigasi daemon version.
Firewall problems:
make sure that the port for the Sigasi FlexLM license daemon is open
you can force the port for the Sigasi license daemon by adding USE_SERVER and DAEMON sigasi port=to your license key
On Linux you might have to install lsb to avoid No such file or directory errors when starting lmgrd or other flexlm tools:
sudo apt-get install lsb-core
zypper in lsb
yum install lsb
yum install redhat-lsb.i686
If the installation of lsb-core fails (e.g. on Debian Linux 10), try this workaround (as root):
cd /lib64
ln -s ld-linux-x86-64.so.2 ld-lsb-x86-64.so.3
The lmgrd license manager needs to have write access to the /usr/tmp/ path. If your system doesn’t have a directory /usr/tmp, you can make a link to /tmp (as root) :
ln -s /tmp /usr/tmp
You can not have spaces in the daemon path.
Some users reported that specifying an arbitrary absolute path for the Sigasi daemon on Windows (e.g. DAEMON sigasi C:\\sigasi.exe port=27021) does not work. It only works if the Sigasi daemon is in the C:\Sigasi folder.
Other users have reported that you are not allowed to have the directory name being the same as the daemon name. For example: c:\flexlm\sigasi\sigasi.exe is invalid, but c:\flexlm\vhdl_editor\sigasi.exe works fine.
Make sure the environment variable is correct: SIGASI_LM_LICENSE_FILE=<port number>@<servername>
Verify that your server meets the License Server System Requirements.
If you try to run the daemon on an unsupported version of Windows, you will typically see this error message: CreateProcess error code: 0xc1 File= sigasi.exe.
You can easily check the status of your license via the License Key preference page : Preferences > Sigasi > License Key. At the bottom of this preference page you can see the type and expiration date of your license.
If you are accessing your license server through an SSH tunnel, try using 127.0.0.1 instead of localhost.
Sigasi Studio pre-emptively tries to check out certain license features. As a result, you might see warning message like this in your server log. These messages can be safely ignored.
9:14:47 (sigasi) UNSUPPORTED: "com.sigasi.hdt.custom" (PORT_AT_HOST_PLUS ) testuser@testmachine (License server system does not support this feature. (-18,327:10054 ""))
9:14:47 (sigasi) UNSUPPORTED: "com.sigasi.hdt.preview" (PORT_AT_HOST_PLUS ) testuser@testmachine (License server system does not support this feature. (-18,327:10054 ""))
If the steps above do not help, feel free to send us an email
and send us a screenshot of the license dialog with the error message.
Typical error messages
Check the content of the Sigasi License preference page via : Window > Preferences and Sigasi > License Key
No license
Is a valid license key path configured (or are valid environment variables used)?
Is the user trying to use a Sigasi Studio 3 license in Sigasi 2.x?
Did you correct the server name to the actual server name in the (floating) license key file?
Internal Flexlm Error
Check version number of FlexNet daemon, it is probably outdated. If not, check the daemon log on the license server
Invalid Message Received From License Server
Check the daemon log on the license server
Updating DACL Failed: “Service has been created but failed to update the DACL settings of FlexNet Licensing Service. It will give problem for accessing TS features. Check whether FlexNet Licensing Service is correctly installed or not and delete and create this service again.”
There seems to be a bug in lmtools.exe version 11 on some systems. You can work around this issue by configuring the (latest) Sigasi daemon with an older version of lmtools (Download here).
(lmgrd) license manager: can’t initialize:No SERVER lines in license file.
(lmgrd) License Path: “C:\FlexLM\sigasi\license.dat”
(lmgrd) FlexNet Licensing error:-13,66
If you see this error message. Double check you license file contains line with USE_SERVER.
FLEXnet Error: “Exiting due to signal 32” (Exited because another server was running)
This error seems to be caused by running multiple instances of license server. If this is the case, first make sure to stop lmtools.exe, lmgrd.exe, and sigasi.exe. If the error still exists after stopping these processes, the real cause might be the name of the FlexLM folder.
If you installed the licensing software under the custom folder C:\FlexLM\, rename the folder to something else, such as C:\LMFlex\. After renaming the folder, also update the path that you set in lmtools “Config Services” tab.
Talkback is a Sigasi Studio service that automatically collects metadata about how Sigasi Studio is used and sends this metadata to Sigasi through a secured connection.
Why should I enable Talkback?
By enabling Talkback you help us improve Sigasi Studio:
Talkback lets us determine which features are heavily used. This helps in planning which kind of features are valuable for you as Sigasi Studio user, so that we can adjust our product roadmap.
Talkback collects performance statistics, that we can relate to the project sizes. Together with our in-house performance tests, this helps us keep the Sigasi Studio compiler and user interface fast.
Talkback helps us reduce software errors by collecting incident reports from a wide range of use cases.
The activation of Talkback is required to enable our free educational and open source licenses.
Talkback is automatic and less cumbersome than feedback surveys.
The end result is that you can use an always-improving Sigasi Studio.
How does Sigasi use this information
Sigasi uses the information transmitted by Talkback for marketing and product planning and development. We use it for deciding which features to develop and improve, for finding and fixing bugs and for finding and fixing performance issues.
What kind of information is sent through Talkback?
Talkback transmits meta-information about your project, operating system, Java Virtual Machine, tool usage, build performance, system statistics, license type, and incident reports (stack traces) that occur due to software errors.
Talkback never transmits any HDL code. All transmissions are through an industry standard SSL secure connection.
In the Talkback transmissions, we identify your Sigasi/Eclipse workspace using a generated identifier (a standard Java universal unique identifier UUID).
Talkback stores all the information it transmits in a local log file, so that you can inspect it. The information is human-readable, in JSON (JavaScript Object Notation) format.
You can access the Talkback log to verify by clicking Window > Preferences > Sigasi > Talkback > Talkback log.
This log file is rotated for each new Sigasi Studio session or when the log reaches a certain size.
How do I enable or disable Talkback?
Talkback is always disabled by default. To enable Talkback, or to disable it later on, do the following.
In Eclipse
Click Window > Preferences > Sigasi > Talkback and select or deselect the checkbox “Enable Talkback”.
In VS Code
Talkback in VS Code only concerns the LSP server process, the client VS Code extension instead uses the Telemetry setting.
Press Ctrl+Shift+P to open the Command Palette
Select Preferences: Open Settings (UI)
In the Setting tab, navigate to Extensions > Sigasi > Enable Talkback
Select or deselect the checkbox
Telemetry
The Sigasi Studio for VS Code will collect telemetry data when an error occurs within the extension itself. This is used to fix bugs and help guide the direction of the product. This is aligned with VS Code’s telemetry and can be tweaked using the VS Code setting: telemetry.telemetryLevel. Note that this VS Code setting is on by default.
For more information regarding telemetry refer to VS Code Telemetry.
What about my Firewall or Proxy?
Talkback uses the https protocol to send the information.
If your firewall blocks SSL connections Talkback will not be able to send diagnostics.
Your firewall should allow outgoing connections to https://talkback-sigasi.sigasi.com/.
Talkback does not support Proxies. If Talkback is unable to connect to our server directly because of your firewall or proxy server, you need to purchase a commercial license.
Features like Talkback are against our corporate policy, even if it is disabled. What can I do?
Please send us an email
so that we can discuss a solution for your company.
The main purpose of HDL languages is to describe a design that would be synthesized and implemented in hardware. However, both VHDL and Verilog also provide additional features for writing verification code to check a design by simulating its behavior. In order to do so you can write testbenches that provide stimulus to DUT inputs and assert if their outputs have unexpected values. More sophisticated language constructs can be used to do more complex checks. The problem with such verification code is that it’s not synthesizable.
You should not use this verification subset of language features in the actual design. For better synthesis Quality of Results (QoR) many other rules should also be followed. However, since these rules only apply to a synthesizable design, there’s usually no need to restrict oneself to following them in verification code.
In order to provide better feedback, Sigasi Studio detects what parts of the code are supposed to be synthesizable and verifies synthesis rules for that code. In order to do so, it detects a description style for design units. The description style can be detected as:
Testbench - top level verification module
Behavioral - additional design units that are supposed to be used for verification purposes
RTL - design units that are part of an actual design that would be synthesized
Sigasi Studio provides the possibility to specify a different severity for rules in RTL and non-RTL (testbench or behavioral) code.
It’s also possible to disable some checks for RTL or non-RTL code by setting the corresponding severity to ignore.
VHDL
In VHDL a description style is detected for every architecture. It’s possible to select how the description style is detected:
Either by detecting verification code
Or based on architecture names
By default, the detecting verification code method is used. In this case, an architecture is detected as:
Testbench, if the corresponding entity does not have any ports, otherwise
Behavioral, if it contains:
non-synthesizable processes, e.g., no sensitivity list or multiple wait statements
uses the std.textio package or declares file types
RTL, in all other cases
This mechanism provides good results in most cases. However, if more fine-grained control is required, you can choose to detect the description style based on architecture names. In this case, you have to specify name patterns that are to be matched against them. An architecture is then detected as:
RTL, if its name matches the valid pattern and does not match the invalid pattern, otherwise
Testbench, if the corresponding entity does not have any ports, or
Behavioral, in all other cases
Verilog
For now, there are no rules that would benefit from a design unit description style, so no detection of description styles is performed.
Libraries View
You can examine the description style detected by Sigasi Studio for VHDL architectures in the Libraries View:
Sigasi Studio’s license key management system is based on the well known FlexNet (a.k.a. FlexLM) license manager.
Sigasi Studio supports both node-locked and floating license keys.
The Sigasi Studio edition is controlled by the license key.
This section details the set-up of the license server when working with floating licenses.
License server setup
Download the FlexNet daemons
The version of the FlexNet daemons must be equal or higher than the FlexLM version of Sigasi Studio. The required version can be found in Sigasi Studio: Window > Preferences > Sigasi > License Key and look for the FLEXLM_VERSION line.
By default, Sigasi license files use ports 27000 and 27001 on your license server.
If these ports are already in use on the server, you can change the port numbers in the license file.
The port of the Sigasi daemon is set on the DAEMON line. For example: DAEMON sigasi port=27001, forces the Sigasi daemon to use port 27001.
The port of the FlexNet daemon is set on the SERVER line For example: SERVER your_server_name1 BD41FCF5DE27 27000, forces FlexNet to use port 27000. This is the port clients need to use to check out a license.
You can change the port numbers and your_server_name1 without breaking the signature.
If you have a firewall, remember to open these ports for access.
Starting the FlexNet and Sigasi daemon on Linux
the easiest way to start the Sigasi FlexNet daemon is like this (on Linux)
Create a folder to hold the license manager software, in this example we will use D:\Sigasi\license.
Unpack the zip file into the license folder (D:\Sigasi\license)
Run the license configuration tool lmtools.exe as administrator.
Save the license file supplied for Sigasi Studio to the license folder
Using a text editor, edit the license file and replace your_server_name1 with the name of the machine you are using, for example, from: SERVER your_server_name1 74e50bb0911e to: SERVER Maple 74e50bb0911e. Note: If you are not sure of the name of the machine you are using click on the System Settings tab of lmtools, where it is shown, see below:
Click on the Config Services tab and fill in the following, use the browse button when available:
Service Name: Sigasi License Manager
Path to lmgrd.exe: D:\sigasi\license\lmgrd.exe
Path to license file: D:\sigasi\license\sigasi.lic
Path to the debug log file: D:\sigasi\license\debug.log Note: You will probably need to type the “Path to the debug log file”, in full as the file will not exist so you cannot browse to it.
Ensure both the following check boxes are checked:
Use Services
Start Server at Power Up
Now click the Save Service button, and click yes on the confirmation dialog.
Switch to the Start/Stop/Reread tab and start the server.
The license server should now be configured correctly, and looks a bit like this one
Troubleshooting
If your license key does not work, the first things to check are:
Which version of the Sigasi license daemon are you using? Note: The Sigasi 2 daemon needs to be updated to run Sigasi 3. Otherwise you will see an License is not valid (Internal Flexlm Error) error message in the Sigasi Studio preference page.
Is the MAC address correct?
Since Sigasi Studio 4.3, on Linux Sigasi Studio uses the ip command to list MAC addresses instead of the now deprecated ifconfig command. If you’re using a version of Sigasi Studio older than 4.3 on Linux, you might need to install additional packages to obtain the ifconfig command.
On Arch, Debian or Ubuntu Linux, the “net-tools” package is needed.
On (Open)Suse the “net-tools-deprecated” package is needed.
Has the license expired?
Did you copy the license string exactly as it was sent to you?
Did you accidentally try to use a License Token as a license key?
A License Token is a 24 character string. You can use your license token to Activate Your License Key.
If your floating license server does not function properly, try the following steps:
Start the FlexLM daemon with the -z option to see what is going wrong
You can check that the FlexNet daemon is running as expected by following these steps:
Download the daemon zip file on the client machine
Run lmutil[.exe] lmdiag -c "<port>@<server>" -n
If the server is running correctly, you should see a description of the valid FlexNet features served by you license server.
Make sure the server name in the license key file is correct.
Make sure both the Sigasi and FlexNet daemon are the same version (i.e. from the same zip-file from the Sigasi download server). If you need to mix versions, the FlexNet daemon version should be equal to or higher than the Sigasi daemon version.
Firewall problems:
make sure that the port for the Sigasi FlexLM license daemon is open
you can force the port for the Sigasi license daemon by adding USE_SERVER and DAEMON sigasi port=to your license key
On Linux you might have to install lsb to avoid No such file or directory errors when starting lmgrd or other flexlm tools:
sudo apt-get install lsb-core
zypper in lsb
yum install lsb
yum install redhat-lsb.i686
If the installation of lsb-core fails (e.g. on Debian Linux 10), try this workaround (as root):
cd /lib64
ln -s ld-linux-x86-64.so.2 ld-lsb-x86-64.so.3
The lmgrd license manager needs to have write access to the /usr/tmp/ path. If your system doesn’t have a directory /usr/tmp, you can make a link to /tmp (as root) :
ln -s /tmp /usr/tmp
You can not have spaces in the daemon path.
Some users reported that specifying an arbitrary absolute path for the Sigasi daemon on Windows (e.g. DAEMON sigasi C:\\sigasi.exe port=27021) does not work. It only works if the Sigasi daemon is in the C:\Sigasi folder.
Other users have reported that you are not allowed to have the directory name being the same as the daemon name. For example: c:\flexlm\sigasi\sigasi.exe is invalid, but c:\flexlm\vhdl_editor\sigasi.exe works fine.
Make sure the environment variable is correct: SIGASI_LM_LICENSE_FILE=<port number>@<servername>
Verify that your server meets the License Server System Requirements.
If you try to run the daemon on an unsupported version of Windows, you will typically see this error message: CreateProcess error code: 0xc1 File= sigasi.exe.
You can easily check the status of your license via the License Key preference page : Preferences > Sigasi > License Key. At the bottom of this preference page you can see the type and expiration date of your license.
If you are accessing your license server through an SSH tunnel, try using 127.0.0.1 instead of localhost.
Sigasi Studio pre-emptively tries to check out certain license features. As a result, you might see warning message like this in your server log. These messages can be safely ignored.
9:14:47 (sigasi) UNSUPPORTED: "com.sigasi.hdt.custom" (PORT_AT_HOST_PLUS ) testuser@testmachine (License server system does not support this feature. (-18,327:10054 ""))
9:14:47 (sigasi) UNSUPPORTED: "com.sigasi.hdt.preview" (PORT_AT_HOST_PLUS ) testuser@testmachine (License server system does not support this feature. (-18,327:10054 ""))
If the steps above do not help, feel free to send us an email
and send us a screenshot of the license dialog with the error message.
Typical error messages
Check the content of the Sigasi License preference page via : Window > Preferences and Sigasi > License Key
No license
Is a valid license key path configured (or are valid environment variables used)?
Is the user trying to use a Sigasi Studio 3 license in Sigasi 2.x?
Did you correct the server name to the actual server name in the (floating) license key file?
Internal Flexlm Error
Check version number of FlexNet daemon, it is probably outdated. If not, check the daemon log on the license server
Invalid Message Received From License Server
Check the daemon log on the license server
Updating DACL Failed: “Service has been created but failed to update the DACL settings of FlexNet Licensing Service. It will give problem for accessing TS features. Check whether FlexNet Licensing Service is correctly installed or not and delete and create this service again.”
There seems to be a bug in lmtools.exe version 11 on some systems. You can work around this issue by configuring the (latest) Sigasi daemon with an older version of lmtools (Download here).
(lmgrd) license manager: can’t initialize:No SERVER lines in license file.
(lmgrd) License Path: “C:\FlexLM\sigasi\license.dat”
(lmgrd) FlexNet Licensing error:-13,66
If you see this error message. Double check you license file contains line with USE_SERVER.
FLEXnet Error: “Exiting due to signal 32” (Exited because another server was running)
This error seems to be caused by running multiple instances of license server. If this is the case, first make sure to stop lmtools.exe, lmgrd.exe, and sigasi.exe. If the error still exists after stopping these processes, the real cause might be the name of the FlexLM folder.
If you installed the licensing software under the custom folder C:\FlexLM\, rename the folder to something else, such as C:\LMFlex\. After renaming the folder, also update the path that you set in lmtools “Config Services” tab.
Sigasi Studio XPRT is the most complete version of Sigasi Studio. It unlocks all features of Sigasi Studio XL
, plus the graphical views, documentation generation, …
Throughout the documentation, features that are only available in this version are marked as [Only in Sigasi Studio XPRT]
.
While support for VHDL-2019 is being improved, this page lists the VHDL-2019 features that are supported in the latest release.
Currently supported
All the new VHDL 2019 APIs in the updated std and ieee libraries
Functions now know the type of the receiver of the return value
functionconvert_to_slv(constanti:ininteger)returnTResultofstd_logic_vectorisvariableresult:TResult;begin-- Can now access attributes of the receiver of this return valueresult:=std_logic_vector(to_signed(i,result'length));returnresult;endfunction;-- Now we can do the followingx<=convert_to_slv(i);-- Instead ofx<=std_logic_vector(to_signed(i,x'length));
The ending component keyword in a component declarations is now optional
A trailing semicolon in port, generic and parameter lists is now allowed
Parameters of impure functions can now have inout and out modes
record declarations can now be empty
Qualified expressions’ operand is now optional
-- Value of "abc" is an empty value of the type std_logicconstantabc:std_logic:=std_logic'();
Improved syntax of power expressions (**)
when-else and unaffected expressions are now allowed in return statements
Sequential block statements
Added an autocomplete for, and improved automatic indentation of, protected type declarations
Added support for VHDL 2019 private variable declaration and aliases in protected declaration
The Sigasi Studio 4.11 release introduced VHDL 2019 into Sigasi Studio.
To make use of the improved language features and APIs you need to set your VHDL project (or a single file) to VHDL 2019 and update the std and ieee libraries:
Update the project version: Right click the project (or file) and select Properties > VHDL Version > VHDL 2019.
Update the std and ieee libraries: Right click the Common Libraries folder, and select Set Library > Reset Common libraries
Although VHDL is not case-sensitive, it is recommended to always use the same capitalization when referring to the same declaration. Sigasi Studio warns when the capitalization of a reference differs from the capitalization of the declaration. Because external libraries can have different code styles, this linting only checks references in the same library as its declaration.
Capitalization can easily be fixed with a Quick Fix.
All capitalization issues in a file can be fixed in one click.
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Sigasi Studio can check that each choice is specified only once in case and case generate statements as well as selected signal and variable assignments.
process is
variable state : std_logic_vector(2 downto 0) := "000";
constant IDLE : std_logic_vector := "110";
begin
case state is
when "000" => state := IDLE;
when "110" => state := "000";
when IDLE => state := "100";
end case;
end process;
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Sigasi Studio gives a warning if a component declaration is not equal to its matching entity. You can easily fix this by applying the Quick Fix.
entity dut is
port(
clk : in std_logic;
rst : in std_logic
);
end entity;
architecture RTL of dut is
component dut
port(
clk : in std_logic;
rst : in std_logic;
dbg : in std_logic
);
end component;
begin
end architecture;
component dut
port(
clk : in std_logic;
rst : in std_logic
);
end component;
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Sigasi Studio can check that header comments of files, design units, subprograms, etc. match specified patterns. A header comment is a comment associated with a declaration or file.
A file header comment starts at the first character of the file (no leading whitespace).
More information on comment association is available here.
The check can be enabled in Preferences > Sigasi > VHDL > Header Comments. The pattern can be set on the same page.
More information on file header comment checking is available here.
Note that the entire comment is checked, including comment characters (-- or /* */).
These characters have to be handled by your patterns too.
Since Sigasi Studio 4.4, the raw string of the header comment is checked to allow for maximum compliance checking.
This means that when a new line is matched, users should use \r?\n or the newly introduced \R to make sure the naming conventions work on all platforms.
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
To prevent issues during synthesis or static timing analysis, it’s important to use a signal that is used as a clock exclusively for that purpose, and not as e.g. reset or data. Sigasi Studio will mark all instances where a clock signal is incorrectly used in this manner.
p : process (clk) is
variable data : std_logic_vector(15 downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
...
else
data(8) := clk;
end if;
end if;
end process p;
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Comparing vectors of different sizes can result in unexpected behavior, and should therefore be avoided. Sigasi Studio will flag all comparisons of vectors whose ranges do not match. Note that potential mismatches will also be flagged when generics are used in one or both of the ranges, more information about such cases can be found in this article.
...
s_in : in std_logic_vector(WIDTH downto 0);
s_out : out std_logic_vector(7 downto 0);
...
if (s_in > s_out) then
...
...
s_in : in std_logic_vector(WIDTH downto 0);
s_out : out std_logic_vector(WIDTH downto 0);
...
if (s_in > s_out) then
...
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Dead code is code that does not have any effect on your simulation or
synthesis. Examples of dead code are signals that are never used or
conditions that are never triggered.
Dead code does not bother the simulator or the synthesis tool. However,
it consumes mental energy of anybody reading the code. People will try
to figure out the purpose of a given statement and it may take a while
before they realize that they are dealing with dead code. This makes it
more expensive to review code and reuse code. In general, dead code
is a form of technical debt that should be avoided.
Sigasi Studio flags some kinds of dead code:
Unused declarations (signals, constants …):
architecture RTL of empty is
signal unused_s : bit;
constant unused_c : bit := '0';
begin end;
A Quick Fix is available to help you remove unused declarations fast.
Unused ports and generics:
entity empty is
generic(unused_g : bit);
port (unused_p : in bit);
end entity;
architecture RTL of empty is begin end;
Unreachable statements: if the Sigasi Studio analyzer can determine that a condition is always false,
it will mark the if-statement because it contains dead code:
if true then
v := v + 1;
elsev := v - 1;
end if;
Dead states in a state machine: a state is considered dead if it has no outgoing transitions:
type t_state is (IDLE, START, RUN, DONE);
signal state: t_state;
-- [omitted code]
case state is
when IDLE => -- do something
state <= RUN;
when RUN => -- do something
state <= DONE;
when DONE => -- do something
state <= IDLE;
when others => -- do nothing
end case;
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
55/severity/${path}={error|warning|info|ignore} # Unused declaration
67/severity/${path}={error|warning|info|ignore} # Unused ports
68/severity/${path}={error|warning|info|ignore} # Unused generics
85/severity/${path}={error|warning|info|ignore} # Unreachable statements
71/severity/${path}={error|warning|info|ignore} # Dead states
Deeply nested conditional and loop statements reduce code readability. Restructuring code or extracting logic to functions can help to keep code in a maintainable state.
Another problem is that deep nesting can result in complicated prioritized logic being synthesized increasing circuit size significantly.
Sigasi Studio can report deeply nested sequential loops and conditions. Note that this rule has the maximum nested depth set to 5 and is ignored by default. You can enable it in the VHDL Errors/Warnings preference page (Style Validation > Deep nesting of conditional and loop statements).
Example with a nesting limit of 2:
procedure nested(a : natural) is
begin
if a >= 1 then -- nesting depth 0
if a < 42 then -- nesting depth 1
for I in 0 to 1 loop -- nesting depth 2
case a is -- Statement exceeds conditional and loop nesting limit of 2
when 21 => report integer'image(a) severity note;
when others => null;
end case;
end loop;
end if;
end if;
end procedure nested;
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
239/severity/${path}={error|warning|info|ignore}
239/param/limit/${path}=${integer} # at least 1
Deprecated IEEE Packages and Non-Standard Packages
Some packages are widely spread but were never standardized by IEEE.
Different vendors have shipped different versions, with incompatible
implementations. These packages should not be used and are flagged as
Deprecated IEEE packages.
use ieee.std_logic_arith.all
use ieee.std_logic_signed.all
use ieee.std_logic_unsigned.all
Instead, use the standard ieee.numeric_std package.
use ieee.numeric_std.all
The package ieee.std_logic_misc has the same problem of not being standardized by IEEE. Contrary to the packages above, there is no consensus on how to replace this package. Sigasi Studio flags this package as Non-standard package.
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
# For deprecated IEEE packages
8/severity/${path}={error|warning|info|ignore}
# For Non-standard packages
37/severity/${path}={error|warning|info|ignore}
Sigasi Studio can check that the filename contains the name of at least one of the design unit names inside that file. Note that this check is ignored by default. You can enable it in the VHDL Errors/Warnings preference page (Style Validation > Filename must contain primary name).
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
When a vector signal is used as a conditional expression or as an argument to logical operators (e.g. &&, ||, !) it’s implicitly converted to scalar value 0 (false) if all vector bits are zero or to 1 (true) otherwise. It’s not clear in this case if such conversion was intentional or by mistake, and a scalar type or bitwise operator, such as &, |, or ~ was expected.
module ff(input clk, [7:0] d, rst, output [7:0] q);
always_ff @(posedge clk) begin
if (rst) // Implicit conversion of 'logic [7:0]' to boolean
q <= 0;
else
q <= !d; // Implicit conversion of 'logic [7:0]' to boolean
end
endmodule
It may be better to explicitly compare the vector with zero (vec == 0 or vec != 0) if that’s your intent.
Note that this rule is disabled (set to IGNORE) by default.
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Sigasi Studio warns about port maps and generic maps that are incomplete: Port map uses default values. Missing optional actuals: yourport
Input ports and generics need to be assigned in your instantiation
statement if they don’t already have a default value. If you don’t do
this, you are writing illegal VHDL. Sigasi Studio will mark an error, and so
will all other tools.
Input ports and generics with a default value, as well as output ports,
do not need to be assigned explicitly. However, this is often not
intended. For that reason, Sigasi Studio can warn you about this.
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
A reset branch should always reset all registers modified by the corresponding clocked block. An incomplete reset branch could cause unexpected enable or clock gating logic to be synthesized for the registers that were not reset. Sigasi will let you know if a reset branch is incomplete, and what registers are missing.
p : process (clk) is
variable a: integer;
variable b: integer;
variable c: integer;
begin
if rising_edge(clk) then
if rst = '1' then -- c is not reset
a := 0;
b := 0;
else
a := a + 1;
b := b + 2;
c := c + 3;
end if;
end if;
end process p;
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Sigasi Studio can check that the same clock edge is used throughout the entire design. It provides a clean coding style simplifying maintainability and enhancing safety. If using a single edge is too restrictive, this rule can be configured to check the clock edge usage consistency for each design file. This rule consists of three check types:
rising, ensures that all clock edges are rising edges
falling, ensures that all clock edges are falling edges
consistent, adapts the rule to the most used edge per design file. If there are equal amounts of rising and falling edges, the first encountered edge will be chosen
The default configured type is consistent, but this can be changed in the Errors/Warnings project setting or workspace preference.
Example with rising edge selected
process(clk) is
variable count : natural := 0;
begin
if rising_edge(clk) then
count := count + 1;
end if;
if falling_edge(clk) then -- Inconsistent!
count := count - 1;
end if;
end process;
Note that this rule also works with the old-school clock edge condition:
process(clk) is
variable count : natural := 0;
begin
if clk'event and clk = '1' then
count := count + 1;
end if;
if clk'event and clk = '0' then -- Inconsistent!
count := count - 1;
end if;
end process;
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
There are two types of resets for a synchronous design, synchronous resets and asynchronous resets. It can be good practice to consistently use only one of these throughout a project. This rule can be configured to prefer either a synchronous or asynchronous reset style and will mark all reset branches that do not follow the selected style.
For example, if the validation is configured to prefer a synchronous reset style:
async_p : process (clk, rst) is
begin
if rst = '1' then
...
elsif rising_edge(clk) then
...
end if;
end process async_p;
sync_p : process (clk) is
begin
if rising_edge(clk) then
if rst = '1' then
...
else
...
end if;
end if;
end process sync_p;
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
VHDL allows arrays with both ascending (to) and descending ranges (downto). For vectors (one-dimensional arrays of scalars, e.g. bit or (u)logic) using a descending range is recommended. In this case leftmost bit is the MSB and the rightmost bit is the LSB, and that is what is assumed by the VHDL standard library’s arithmetic operators. Using an ascending range for vectors is also possible, however, it’s recommended to use a consistent style.
entity Downto_vectors is
port(
G0_g : bit_vector(0 to 7);
G1_g : bit_vector(7 downto 0);
);
end entity Downto_vectors;
This rule can be configured by setting the desired vector range direction, either ascending or descending.
Note that this rule is set to
ignore by default.
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Sigasi Studio lets users restrict the usage of language features.
Prohibited Keyword or Operator
Keywords and operators can be restricted using a list of keywords and operators that cannot be used (rule 245). For example:
Following keywords and operators are not allowed: **, after
if a**2=4 then -- Operator '**' is prohibited
a <= 8 after 5 ns; -- Keyword 'after' is prohibited
end if;
Prohibited Attribute
Attributes can be restricted using a list of attributes that cannot be used (rule 243). These attributes can be configured in two modes: deny and allow, and can also include checks for user-defined attributes. For example:
Check attributes in deny mode (event and value denied)
architecture RTL of prohibited_attribute is
begin
a : process is
type myEnum is (a, b, c, d);
constant constB : myEnum := myEnum'value("b"); -- Attribute 'value' is prohibited
begin
if clk'event then -- Attribute 'event' is prohibited
report "event" severity note;
end if;
if clk'low = '1' then -- Attribute 'low' is allowed
report "low" severity note;
end if;
end process a;
end architecture RTL;
Check attributes in allow mode (event allowed)
architecture RTL of allowed_attribute is
begin
a : process is
type myEnum is (a, b, c, d);
constant constB : myEnum := myEnum'value("b"); -- Attribute 'value' is prohibited
begin
if clk'event then -- Attribute 'event' is allowed
report "event" severity note;
end if;
end process a;
end architecture RTL;
Prohibited Library
Libraries can be restricted using a list of denied or allowed libraries that will be reported in the use clause (rule 248). Using the current work library is always allowed regardless of configuration. For example:
Library abcdenied
library abc; -- Library 'abc' is prohibited
Library ieeeallowed
library abc; -- Only library 'ieee' is allowed
Prohibited Package
Packages can be restricted using a list of denied or allowed packages that will be reported in the use clause (rule 246). Using packages from the work library or the current work library is always allowed regardless of configuration. For example:
Check packages in deny mode (ieee.numeric_std and work.user_package denied)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- Package 'numeric_std' is prohibited
use work.user_package.all; -- Ignored because work
Check packages in allow mode (ieee.numeric_std and work.user_package allowed)
library ieee;
use ieee.std_logic_1164.all; -- Package 'std_logic_1164' is prohibited
use ieee.numeric_std.all;
use work.user_package.all; -- Ignored because work
Check packages in denied mode, with the current file mapped to the library memory(memory.ram_cell denied)
library ieee, memory;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use memory.ram_cell.all; -- Ignored because mapped to the same library
Prohibited Pragma
Pragmas can be restricted using a list of pragmas that will be reported when they are used (rule 247). For example:
The following pragma is not allowed: vhdl_comp_off
-- vhdl_comp_off -- Pragma 'vhdl_comp_off' is prohibited
assert (rst_lvl = 0) or (rst_lvl = 1)
report "rst_lvl should be 0 or 1"
severity failure;
-- vhdl_comp_on
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
Sigasi Studio can check for a number of array / vector index-related problems:
Index out of range (rule 210).
architecture RTL of array_range_check is
signal foo: bit_vector(7 downto 0);
signal bar, baz: bit;
begin
bar <= foo(8); -- 8 is out of range "7 downto 0"
baz <= foo(7);
end architecture RTL;
Slice has wrong direction (rule 211).
Slice ranges must use the same direction as the vector.
architecture RTL of array_range_check is
constant iterations : integer := 8;
signal foo: bit_vector(7 downto 0);
signal bar, baz: bit_vector(0 to 7);
begin
bar <= foo(0 to 7); -- foo has a downto range
baz <= foo;
end architecture RTL;
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
Sigasi Studio can check for a number of problems related to deferred constants that the VHDL language reference mandates:
Duplicate declaration
A deferred constant cannot reassign its initial value to a different value (rule 54).
package pkg is
constant foo : integer := 2;
constant bar : boolean;
end package;
package body pkg is
constant foo : integer := 3; -- foo was already assigned a value
constant bar : boolean := false;
end package body;
Missing full constant declaration
If a constant declaration in a package has no initial value, it shall have a deferred constant declaration in the package body with a matching initial value (rule 233).
package pkg is
constant a : integer;
constant b, c : boolean;
end package;
package body pkg is
constant a : integer := 3;
constant b : boolean := false; -- c was not assigned a value
end package body;
Incorrect full constant declaration subtype
The type of a deferred constant declaration in the package body must match the type of the constant declaration in the package (rule 234).
package pkg is
constant foo : boolean;
constant bar : integer;
end package;
package body pkg is
constant foo : integer := 8; -- foo was declared as a boolean in the package
constant bar : integer := 7;
end package body;
It can be good practice to separate the primary units in a design and declare them in separate files.
Similarly, guidelines exist for where secondary units should be declared in relation to other secondary units or to their corresponding primary unit.
Sigasi Studio can enforce where design units are defined in relation to other design units.
File contains multiple primary units
Every primary unit should live in a separate file.
package pkg1 is
end package;
package pkg2 is -- more than 1 primary unit in the file
end package;
Secondary unit in unexpected file
Secondary units are more flexible. Sigasi can suggest to put them either
in the same file as their corresponding primary unit, or in a separate
file (or not check them at all). You can configure this separately
for the architecture of entities with a single architecture, for the
architectures of an entity with multiple architectures, and for package
bodies.
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
# Primary unit location
242/severity/${path}={error|warning|info|ignore}
# Secondary unit location
243/severity/${path}={error|warning|info|ignore}
243/param/single_architecture/${path}={same_file_as_primary|separate_file|ignore}
243/param/multiple_architectures/${path}={separate_file|same_file_as_primary|ignore}
243/param/package_body/${path}={separate_file|same_file_as_primary|ignore}
Sigasi Studio can check for a number of loop-related problems:
Infinite loop missing a wait (rule 20). Note that infinite while and for loops will not be checked by this rule.
process
begin
loop
-- statements go here
end loop;
end process;
process
begin
loop
-- statements go here
wait for 1 ns;
end loop;
end process;
Empty loop statement (rule 190): the loop body doesn’t contain any statements
for loopvar in loop
-- nothing going on here...
end loop;
for loops that will not execute due to a loop variable with a null range will be flagged with the Null range linting rule.
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
It is advised not to use multiple-object declarations. It’s better to split declared objects into an equivalent sequence of single-object declarations instead. This practice enhances readability and makes it easier to manage and maintain your code.
Sigasi Studio warns the user when multiple objects are declared within a single declaration.
entity t is
generic(
DATA_WIDTH, ADDR_WIDTH: integer
);
port(
a: in std_logic(DATA_WIDTH - 1 downto 0); -- first operand
b: in std_logic(DATA_WIDTH - 1 downto 0) -- second operand
);
end entity t;
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
On the Naming Conventions preference page (Window >
Preferences > Sigasi > VHDL|Verilog/SystemVerilog > Naming Conventions) you can configure
patterns to check the correct naming of your VHDL, Verilog, and SystemVerilog identifiers. Two patterns can be set for an identifier: a valid pattern that the name of the identifier should match, and an invalid pattern that the name shouldn’t match.
An identifier has to fulfill both conditions, so a name that matches both patterns is not valid.
Patterns are configured using regex syntax.
Note: The Naming Conventions preference page is not yet available in the project preferences.
If you require project-based configuration of the naming conventions rather than workspace preferences,
please refer to the manual Rule configuration detailed below.
Only names with a specified pattern are checked. Empty patterns are omitted.
Example: to enforce a style where all variables have a _v suffix, and don’t contain numbers,
you would specify .*_v for the valid pattern and .*[0-9].* for the invalid pattern in the Variable name field.
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
# Note: two patterns can be specified. These patterns are separated by a tab
# character. The first pattern specifies a *valid* pattern (something that must
# match), and the second pattern specifies an *invalid* pattern (something that
# can not match). If only a valid pattern is required, the tab character can
# be left out. If only an invalid pattern is required, the pattern should be
# specified after a (backslash-escaped) tab character.
# In the VHDL linting preferences file
92/severity/${path}={error|warning|info|ignore}
92/params/alias_name/${path}=${regex} ${regex}
92/params/architecture_name/${path}=${regex} ${regex}
92/params/comment_header/${path}=${regex} ${regex}
92/params/concurrent_assignment_name/${path}=${regex} ${regex}
92/params/configuration_name/${path}=${regex} ${regex}
92/params/constant_name/${path}=${regex} ${regex}
92/params/context_declaration/${path}=${regex} ${regex}
92/params/entity_name/${path}=${regex} ${regex}
92/params/enumeration_literal_name/${path}=${regex} ${regex}
92/params/file_name/${path}=${regex} ${regex}
92/params/fsm_enumeration_literal_name/${path}=${regex} ${regex}
92/params/fsm_state_name/${path}=${regex} ${regex}
92/params/function_name/${path}=${regex} ${regex}
92/params/generate_statement_name/${path}=${regex} ${regex}
92/params/generic_name/${path}=${regex} ${regex}
92/params/instantiation_statement_name/${path}=${regex} ${regex}
92/params/label/${path}=${regex} ${regex}
92/params/package_name/${path}=${regex} ${regex}
92/params/procedure_name/${path}=${regex} ${regex}
92/params/port_name/${path}=${regex} ${regex}
92/params/input_port_name/${path}=${regex} ${regex}
92/params/output_port_name/${path}=${regex} ${regex}
92/params/inout_port_name/${path}=${regex} ${regex}
92/params/process_statement_name/${path}=${regex} ${regex}
92/params/signal_name/${path}=${regex} ${regex}
92/params/type_name/${path}=${regex} ${regex}
92/params/variable_name/${path}=${regex} ${regex}
# In the Verilog linting preferences file
2/severity/${path}={error|warning|info|ignore}
2/params/class_name/${path}=${regex} ${regex}
2/params/comment_header/${path}=${regex} ${regex}
2/params/instantiation/${path}=${regex} ${regex}
2/params/interface_class_name/${path}=${regex} ${regex}
2/params/interface_name/${path}=${regex} ${regex}
2/params/module_name/${path}=${regex} ${regex}
2/params/package_name/${path}=${regex} ${regex}
2/params/program_name/${path}=${regex} ${regex}
2/params/subprogram_name/${path}=${regex} ${regex}
2/params/port_name/${path}=${regex} ${regex}
2/params/input_name/${path}=${regex} ${regex}
2/params/output_name/${path}=${regex} ${regex}
2/params/inout_name/${path}=${regex} ${regex}
2/params/parameter_name/${path}=${regex} ${regex}
2/params/net_name/${path}=${regex} ${regex}
2/params/var_name/${path}=${regex} ${regex}
2/params/ud_nettype_name/${path}=${regex} ${regex}
2/params/typedef_name/${path}=${regex} ${regex}
2/params/enum_typedef_name/${path}=${regex} ${regex}
2/params/enum_member_name/${path}=${regex} ${regex}
2/params/generate_block_name/${path}=${regex} ${regex}
Example
A manual VHDL configuration were all ports must start with p_
except inout ports which must start with b_,
and where input ports cannot contain numbers.
We mark the ports with error markers if they don’t comply.
In VHDL, you can use ranges with to and downto. But, if you use the
wrong direction, you get an empty range, which is usually not what you
want.
signal foo: std_logic_vector(7 downto 0) -- range of 8;
signal foo: std_logic_vector(7 to 0) -- null range;
We have a lint check that warns about this, even if you use constants or some simple arithmetic.
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
# For ascending ranges
1/severity/${path}={error|warning|info|ignore}
# For descending ranges
26/severity/${path}={error|warning|info|ignore}
Sigasi Studio gives a warning when the order of generics or ports in a map differs from the original generics or ports declaration order.
architecture RTL of dut is
component my_comp port (
clk : in std_logic;
rst : in std_logic;
inp : in std_logic;
outp : out std_logic);
end component;
begin
assert iterations <= MAX_COUNT;
i_comp_1: my_comp port map( -- associations should be kept in the same order as the declaration
rst => rst,clk => clk,
inp => data_in(0),
outp => open
);
i_comp_1: my_comp port map(
clk => clk,rst => rst,
inp => data_in(0),
outp => open
);
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Most VHDL designers prefer named associations in port and generic maps in instantiations. This makes it a lot easier to spot wrong connections.
By default, Sigasi Studio warns when positional associations are used. You can change the severity of this check via Preferences > Sigasi > VHDL > Errors/Warnings in the Instantiation statement validation section.
architecture RTL of dut is
component my_comp port (
clk : in std_logic;
rst : in std_logic;
inp : in std_logic;
outp : out std_logic);
end component;
begin
i_comp_1: my_comp port map( -- positional associations not recommended
clk,rst,data_in(0),open
);
i_comp_2: my_comp port map( -- named associations recommended
clk => clk,rst => rst,inp => data_in(0),outp => open
);
end architecture RTL;
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
If you are using vendor libraries from Intel or AMD/Xilinx (ISE or Vivado),
you do not need to set up these libraries by hand. Sigasi Studio has a Quick Fix
to do this for you.
The missing library will be added to the Common Libraries of your project.
The library statement that tries to import a missing library (like
altera) will have a yellow warning marker next to it. Click this
marker and select Configure library altera (Altera). If the path to your
Intel Quartus (or AMD/Xilinx ISE or Vivado) installation is not yet set, Sigasi Studio will
ask to set the path now. You can always change these paths in Window
> Preferences > Sigasi > Toolchains.
Note that for the AMD/Xilinx libraries we only map the packages with the
component declarations. By default, all entity and architecture
declarations are not mapped (excluded). This significantly reduces the
time for a clean build. If you use direct entity instantiations, you can
easily map the entities you need.
See also Choose your version of the Vivado unisim.VCOMPONENTS package.
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
If a case statement contains all the possible choices (usually in an
enumerated datatype), you can safely remove the when others clause.
Sigasi Studio warns about this:
Case statement contains all choices explicitly. You can safely remove
the redundant others.
case bits is
when "00" => -- code
when "01" => -- code
when "10" => -- code
when "11" => -- code
when others => -- never reached: all cases are covered
end case;
There is some debate on this coding rule. However, the vast majority of
synthesis tools do not take the others into account if all choices are
enumerated. If the synthesis tool is set up to generate fault-tolerant
hardware, the fallback state is the same as the reset state (for most
synthesis tools). Check the manual of your synthesis tools and run some
experiments.
For more information, see VHDL case statements can do without the “others”.
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Sigasi Studio can warn about problems with your sensitivity list:
Presence of either a sensitivity list or one or more wait statements in a process
VHDL requires a sensitivity list for each process or wait statements in the process body.
Incomplete sensitivity list
A sensitivity list should contain all signals the process is sensitive to.
process(a)
begin
c <= a and b;
end process;
Superfluous signals in sensitivity list
A sensitivity list should only contain signals the process is sensitive to. Adding more signals will only slow down your simulations.
process(a, b, c)
begin
c <= a and b;
end process;
Duplicate signals in sensitivity list
A sensitivity list should only contain signals the process is sensitive to. Adding duplicate signals is likely a typo and doesn’t have any practical effect.
process(a, b, b)
begin
c <= a and b;
end process;
A sensitivity list should contain all signals that are read
asynchronously in the process. For a combinatorial process, all
signals read by the process should be in the sensitivity list. For a
synchronous or clocked process, only the clock signal and an
asynchronous reset signal (if present) should be in the sensitivity
list. In synthesizable code, an incomplete sensitivity list will
likely cause a synthesis-simulation mismatch. Even in test benches and
purely behavioral code, an incomplete sensitivity list is often
unintended and may lead to an unexpected simulation result. Most
synthesis tools ignore the sensitivity list. In traditional workflows,
only the synthesis warnings will give you a hint that your sensitivity
list is incomplete. This report will be available only hours or even
days after you have finished typing your code. Flagging this problem
early can save a lot of time.
Since VHDL-2008, you can write process (all) to make sure you have
all the necessary signals in the sensitivity list.
process(a, b)
begin
c <= a and b;
end process;
process(clk)
begin
if rising_edge(clk) then
-- code
end if;
end process;
process(clk, rst)
begin
if rst = '1' then
-- reset code
elsif rising_edge(clk) then
-- code
end if;
end process;
process(all)
begin
c <= a and b;
end process;
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
38/severity/${path}={error|warning|info|ignore} # Neither sensitivity nor wait
72/severity/${path}={error|warning|info|ignore} # Incomplete sensitivity list
73/severity/${path}={error|warning|info|ignore} # Superfluous signals
85/severity/${path}={error|warning|info|ignore} # Duplicate signals
If you type a numeric literal with a physical unit, there should be a
space between the number and the unit.
T := 25ns; -- ILLEGAL, but accepted by ModelSim
T := 25 ns; -- OK; according to VHDL language standard
Mentor Graphics’ ModelSim and QuestaSim accept the former (illegal)
version. As a result, some VHDL designers got used to writing the
incorrect version, producing code that is not portable to other
simulators. Sigasi Studio accepts the ModelSim-style physical literals
but warns about this (rule 47).
Every design unit except package STANDARD is assumed to contain the following implicit context items as part of its context clause:
librarySTD,WORK;useSTD.STANDARD.all;
Hence, any extra library statement in your VHDL code that includes
STD or WORK is pointless, as is any use clause that includes
std.standard.all. Hardly anybody would type the use clause, but
quite some people start all of their files with two extra library
clauses.
It is good practice not to include use clauses for libraries STD and WORK. Sigasi Studio flags as warning if they appear.
library IEEE, STD, WORK;
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
When using booleans, it is unnecessary to test whether they’re equal to true (rule 185) or false (rule 186). Simply testing the boolean results in cleaner code.
signal valid: boolean;
-- some code omitted
if valid then
-- ...
end if;
if valid = true then
-- ...
end if;
if not valid then
-- ...
end if;
if valid = false then
-- ...
end if;
if valid /= true then
-- ...
end if;
Note that the equals-false rule (186) is disabled (set to IGNORE) by default.
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
Different EDA tools have extended the Verilog and SystemVerilog
standard in diverging ways. To maximize tool compatibility, Sigasi
allows some constructs not included in the standards. The linting rules
listed below mark the usage of such constructs as a warning, which can
be disabled individually if you use a tool that allows a particular
construct.
Whitespace following a backtick
Some tools allow additional whitespace following the backtick of a preprocessor directive.
`define A 1
` define B 2 /* unexpected whitespace following the backtick */
Invalid preprocessor syntax
Some directives and escape sequences such as `` and
`" can only be used inside the body of a macro definition.
Some tools are however more lenient, allowing them also elsewhere.
var asdf = `"asdf"; // Unexpected `" directive outside macro body
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
117/severity/${path}={error|warning|info|ignore} # Whitespace following a backtick
121/severity/${path}={error|warning|info|ignore} # Invalid preprocessor syntax
Sigasi Studio flags an error if a type is used in an expression (rule 209).
architecture RTL of type_in_expr is
type t_foo is (one, two);
begin
p : process is
begin
case t_foo is -- a type cannot be used in an expression e.g. a case expression
when one =>
end case;
end process p;
end architecture RTL;
architecture RTL of type_in_expr is
type t_foo is (one, two);
signal s_foo: t_foo;
begin
p : process is
begin
case s_foo is -- use a signal or variable of the required type in expressions
when one =>
end case;
end process p;
end architecture RTL;
In VHDL, it is good practice to constrain integer types (or types derived from integer types) when they are used for signals. Doing so will allow the synthesis tool to optimize the number of bits used for this signal. If this rule is enabled, Sigasi will report all unconstrained integer types used for signals.
...
signal sig_a : integer;
signal sig_b : integer range 0 to 100;
...
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Sigasi Studio can check that the same clock edge specification style is used throughout the entire design. This standard rule provides a clean coding style guaranteeing consistency in clock checks. This rule consists of three configurable options:
event attribute, ensures that all clock conditions are using the event attribute, for example, clk'event and clk = '1'
stable attribute, ensures that all clock conditions are using the stable attribute, for example, not clk'stable and clk = '1'
edge function (the default), ensures that all clock conditions are using an edge function, for example, rising_edge(clk)falling_edge(clk)
Example with “edge function” selected
process(clk) is
variable count : natural := 0;
begin
if clk'event and clk='0' then -- Wrong clock style!
count := count + 1;
end if;
end process;
process(clk) is
variable count : natural := 0;
begin
if falling_edge(clk) then
count := count - 1;
end if;
end process;
Note that using clock attributes is deprecated since VHDL 93 by the IEEE 1164 standard, use edge functions instead.
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
It is recommended to declare the FSM states as enumerated data types. Enumerated state types make HDL code generally more readable. It also facilitates increased flexibility in the synthesis implementation as you can select the encoding style used without modifying the HDL code. These aspects support greater design portability and support FSM error detection and recovery.
In safety-critical designs though, std_logic_vector can still be preferred.
Sigasi Studio can ensure one of the following types is used for FSM state signals or variables:
enumeration
arrays of (u)logic, e.g., std_logic_vector
arrays of bit, e.g., bit_vector
The type that is configured by default is “enumeration”.
Example with “array of logic” as expected FSM state type:
process is
variable state : bit_vector(1 downto 0) := "00"; -- Unexpected FSM state type: expected array of (u)logic but was 'bit_vector'
variable state2 : std_logic_vector(1 downto 0) := "00";
begin
case state is
when "00" => state := "11";
when "11" => state := "00";
end case;
end process;
Note that this rule is set to
ignore by default. You can enable it in the VHDL Errors/Warnings preference page (Style Validation > Unexpected FSM state type).
You can also configure the FSM state type that is checked on this page.
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
VHDL is mostly a case-insensitive language, so keywords can be written in any case: lowercase, uppercase, or any combination of those. Using a consistent casing for keywords throughout the project may improve readability.
signal lower: boolean;
Signal mixed: boolean;
SIGNAL upper: boolean;
This rule can be configured by setting the desired default capitalization: either lowercase, uppercase, or consistent in file. The latter will look at the majority of casing in the file. Some specific keyword capitalization exceptions can also be added.
Note that this rule is set to
ignore by default.
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
SystemVerilog allows the use of vector types as edge event expressions. However, in this case, the transition would be detected only for the least significant bit of the vector. Edge detection is usually used for clocks and asynchronous reset signals which are supposed to be scalar. Sigasi Studio reports usages of vectors in edge event controls, as they’re most likely an indication of signal name typo or an incorrect data type of a control signal.
module ff(input [7:0] d, clk, output [7:0] q);
always_ff @(posedge clk) begin // Edge event detection on 'logic [7:0]'. Only changes to the LSB of the vector will be detected
q <= d;
end
endmodule
If detecting the edge on a single bit of the vector signal is intentional, using bit-selection can show this decision explicitly:
module ffs#(WIDTH = 8) (input [WIDTH-1:0] d, clk, output [WIDTH-1:0] q);
for (genvar i = 0; i < WIDTH; i++) begin
always_ff @(posedge clk[i]) begin
q[i] <= d[i];
end
end
endmodule
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Sigasi Studio checks the vector size in assignments and port maps. This check works at type-time and takes the (symbolic) value of generics into account.
Sigasi Studio will not take into account the value assigned to a generic in instantiations. The reasoning behind this is explained here.
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
In Verilog, it is possible to reference identifiers from different files. However, if multiple files are declaring the same identifier there is no way to know which one should be used. Such cases will be marked as ambiguous references (rule 93).
A possible reason you might be seeing these errors is that your project defines multiple top levels that have been mapped to the same library. More information about library mappings can be found here.
Sigasi Studio has several checks on Verilog assignment patterns.
Default member must be last
Concrete assignments must precede more general assignments. Otherwise, some of those assignments might be ignored (rule 28).
In particular:
for arrays, default must be at the end of the list
for structures, default must be at the end, but type-default must be after the particular member assignments
module badcode;
int a[3:0] = '{0: 5, default: 0, 3: 1};
typedef struct {
int x;
int y;
real radius;
} circle_t;
circle_t b = '{default: 0, x:1};
circle_t c = '{default: 0, real: 0.0};
endmodule
module goodcode;
int a[3:0] = '{0: 5, 3: 1, default: 0};
typedef struct {
int x;
int y;
real radius;
} circle_t;
circle_t b = '{x:1, default: 0};
circle_t c = '{real: 0.0, default: 0};
endmodule
Only one default member expression is allowed
Sigasi Studio flags an error when expressions have multiple default assignments (rule 29). In particular:
arrays cannot have multiple default assignments
structures cannot have multiple default assignments or multiple type-default assignments
module badcode;
int a[3:0] = '{default: 1, 0: 2, default: 3}; // multiple default assignments
typedef struct {
int x;
int y;
real radius;
} circle_t;
circle_t b = '{default: 0, radius: 1.0, default: 0}; // multiple default assignments
circle_t c = '{int: 0, radius: 1.0, int: 0}; // multiple *type*-default assignments
endmodule
module goodcode;
int a[3:0] = '{0: 2, default: 3};
typedef struct {
int x;
int y;
real radius;
} circle_t;
circle_t b = '{radius: 1.0, default: 0};
circle_t c = '{radius: 1.0, int: 0};
endmodule
Overwritten type key in assignment pattern
Sigasi Studio warns about duplicate type member keys in assignment patterns (rule 30). This is not an error according to the language reference manual,
but the last used type key overwrites previously matched members, making the code confusing and hard to maintain.
module uglycode;
struct { int x, y; } a = '{int: 0, int: 1};
int b[10] = '{int: 0, int: 1};
endmodule
module goodcode;
struct { int x, y; } a = '{int: 1};
int b[10] = '{int: 1};
endmodule
Duplicate member key in structure assignment pattern
Sigasi Studio flags an error for duplicate members/index keys in assignment patterns (rule 31). Each member/index key can occur only once.
module badcode;
struct { int x, y; } a = '{x: 0, y: 0, x: 0};
int b[10] = '{5: 1, 5: 2, default: 0};
endmodule
module goodcode;
struct { int x, y; } a = '{x: 0, y: 0};
int b[10] = '{5: 1, default:0};
endmodule
Mixed named and ordered notation in assignment pattern
Sigasi Studio flags an error when an assignment contains a mix of ordered and named elements (rule 32).
module badcode;
// Mix of ordered and named associations: not correct
struct { int x, y; } a = '{0, y: 1};
int b[4] = '{0, 1, 2:5, 3:7};
endmodule
module ok_code;
// Place binding: correct but may be harder to read, particularly with many elements
struct { int x, y; } a = '{0, 1};
int b[4] = '{0, 1, 5, 7};
endmodule
module goodcode;
// Name binding: esay to understand and maintain
struct { int x, y; } a = '{x: 0, y: 1};
int b[4] = '{0: 0, 1: 1, 2: 5, 3: 7};
endmodule
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
28/severity/${path}={error|warning|info|ignore} # default member must be last
30/severity/${path}={error|warning|info|ignore} # overwritten type key in assignment pattern
31/severity/${path}={error|warning|info|ignore} # duplicate member key in structure assignment pattern
32/severity/${path}={error|warning|info|ignore} # mixed named and ordered notation in assignment pattern
Sigasi Studio has a number of checks on Verilog case statements.
Case statement does not cover all cases
A case statement should cover all options, either enumerating all options explicitly or with a default
clause (rule 8). This rule is checked for enum types only, not for scalar or vector types.
module badcode(input clk);
typedef enum {INIT, IDLE, START, READY} t_state;
t_state state;
always @(posedge clk) begin
case (state) // Error: case `INIT` is missing
IDLE : state = START;
START : state = READY;
READY : state = IDLE ;
endcase
end
endmodule
module bettercode(input clk);
typedef enum {INIT, IDLE, START, READY} t_state;
t_state state;
always @(posedge clk) begin
case (state)
INIT : state = IDLE ;
IDLE : state = START;
START : state = READY;
READY : state = IDLE ;
endcase
end
endmodule
Default clause has to be the last item in a case statement
The default clause should be at the end after all the other options (rule 15). Sigasi Studio warns if that is not the case.
module badcode(input clk);
typedef enum {INIT, IDLE, START, READY} t_state;
t_state state;
always @(posedge clk) begin
case (state)
IDLE : state = START;
START : state = READY;
default : state = IDLE ; // The `default` clause must be at the end
READY : state = IDLE ;
endcase
end
endmodule
module goodcode(input clk);
typedef enum {INIT, IDLE, START, READY} t_state;
t_state state;
always @(posedge clk) begin
case (state)
IDLE : state = START;
START : state = READY;
READY : state = IDLE ;
default : state = IDLE ;
endcase
end
endmodule
This rule also applies to generate case statements, e.g.
module bad_example#(parameter WIDTH=8);
generate
case (WIDTH)
default: // The `default` clause must be at the end begin // others - carry look-ahead adder
adder_cla #(WIDTH) x3(co, sum, a, b, ci); end
1: begin // 1-bit adder implementation
adder_1bit x1(co, sum, a, b, ci);
end
// other cases
endcase
endgenerate
endmodule
Case statement can only have one default clause
A case statement can only have one default clause (rule 16). A warning is flagged if more than one default clause is present.
module badcode(input clk);
typedef enum {INIT, IDLE, START, READY} t_state;
t_state state;
always @(posedge clk) begin
case (state)
IDLE : state = START;
START : state = READY;
READY : state = IDLE ;
default : state = IDLE ; // Error: two `default` clauses
default : state = START;
endcase
end
endmodule
module goodcode(input clk);
typedef enum {INIT, IDLE, START, READY} t_state;
t_state state;
always @(posedge clk) begin
case (state)
IDLE : state = START;
START : state = READY;
READY : state = IDLE ;
default : state = IDLE ;
endcase
end
endmodule
This rule also applies to generate case statements, e.g.
module bad_example#(parameter WIDTH=8);
generate
case (WIDTH)
default: // Error: two `default` clauses begin // others - carry look-ahead adder
adder_cla #(WIDTH) x3(co, sum, a, b, ci); end
1: begin // 1-bit adder implementation
adder_1bit x1(co, sum, a, b, ci);
end
// other cases
default: // Error: two `default` clauses begin // others - carry look-ahead adder
adder_cla #(WIDTH) x3(co, sum, a, b, ci); end
endcase
endgenerate
endmodule
Default clause missing from case statement
Sigasi Studio warns for case statements without a default clause (rule 40). While a case statement without a default branch is syntactically correct, many guidelines recommend attaching a default branch, even if the case statement is completely defined. This ensures no latch would be inferred during synthesis if the case is incomplete (sometimes difficult to judge, esp with casex/casez semantics or larger widths).
module rather_ok_code(input clk);
typedef enum {INIT, IDLE, START, READY} t_state;
t_state state;
always @(posedge clk) begin
case (state)
INIT : state = IDLE ;
IDLE : state = START;
START : state = READY;
READY : state = IDLE ;
// no default branch
endcase
end
endmodule
module goodcode(input clk);
typedef enum {INIT, IDLE, START, READY} t_state;
t_state state;
always @(posedge clk) begin
case (state)
INIT : state = IDLE ;
IDLE : state = START;
START : state = READY;
READY : state = IDLE ;
default : state = IDLE ;
endcase
end
endmodule
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
8/severity/${path}={error|warning|info|ignore} # Missing cases
15/severity/${path}={error|warning|info|ignore} # Default clause must be last
16/severity/${path}={error|warning|info|ignore} # Multiple default clauses
40/severity/${path}={error|warning|info|ignore} # Missing default clause
Initializing registers at the point of declaration may be tricky. If your (System)Verilog code is not going
to be synthesized (e.g. testbench), it is completely acceptable. FPGA synthesis tools may also take initialization
into account, so depending on your FPGA project, initializing registers when they are declared in the code may be
a viable (or even preferred) option.
ASIC synthesis tools however will ignore initialization as in the first example, which may lead to a mismatch between
synthesis and simulation. In such a case, initialization should be done using resets, as in the second example.
By default, Sigasi Studio warns for register initialization at the point of the declaration. For FPGA projects
it may be desirable to turn the warning off, whereas for ASIC projects one may want to raise the severity to error.
module fpga_only(input clk, input rst, input ii, output logic oo = 1'b0);
logic sig = 1'b0;
// ...
endmodule
module asic_fpga(input clk, input rst, input ii, output logic oo);
logic sig;
always @(posedge clk) begin
if (rst == 1) beginsig = 1'b0;oo = 1'b0;end
else begin
// ...
end
end
endmodule
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
In Verilog class methods and class properties can be declared as local or protected to restrict their access. Sigasi Studio will flag attempted accesses that violate these restrictions as errors (rule 61).
Local
local methods and properties can only be accessed from within the class itself.
class my_class;
local int secret = 42;
function int get_secret();
return secret;
endfunction
endclass
module bad_code;
my_class inst = new();
int x = inst.secret;
endmodule
Protected
protected methods and properties can only be accessed from within the class itself, or from any of its subclasses.
class my_class;
protected int secret = 42;
endclass
class my_sub_class extends my_class;
function int get_secret();
return secret;
endfunction
endclass
module bad_code;
my_sub_class inst = new();
int x = inst.secret;
endmodule
Sigasi Studio has a number of checks on Verilog and SystemVerilog coding style.
Empty loops and conditional branches
While occasionally intended, this construction is confusing, and often
the result of a typo. Sigasi will flag a warning if an empty block is
found (rule 1). In RTL code for synthesis, empty conditional branches
in sequential code can cause unwanted latch generation. There may
be a couple of reasons why an empty block is present in your code:
It is an unintentional omission and should be fixed to prevent unexpected behavior.
Some functionality is not yet, or never will be, supported. In this case, a $fatal (or similar) system task should be called.
It is intentionally blank. In this case, a comment should clarify the reason why.
File name does not match design unit
It is recommended that the base name of the filename is the same as the name of the design unit (e.g. module) in the file (rule 17). Sigasi Studio warns if that is not the case.
For example, module my_module should be in a file named my_module.v or my_module.sv .
In a file with multiple design units (which is not recommended), this rule is not active.
File contains multiple design unit
It is recommended that a Verilog file contains only one design unit (rule 18). Sigasi Studio warns if that is not the case.
module foo;
endmodule
module bar;
endmodule
Verilog code line too long
For legibility, it is recommended to keep lines of code short (rule 20). Sigasi Studio warns if a code line is longer
than a certain length. The maximum length is set to 120 characters by default, but this can be changed in the
project linting settings.
Tabs are not allowed
While this may potentially be controversial, TABs are forbidden in the majority of coding standards in the HDL domain with the motivation
of code not looking the same regardless of the editor/settings used. This check is set to
ignore by default but it can be enabled in
the workspace or project linting settings (rule 21).
File header comment does not match required pattern
Many coding standards require the presence of a header comment in every file, matching a certain format. Sigasi Studio can check whether the file
header comment matches a pattern (rule 22). By default, the pattern is empty which disables this check.
The pattern can be configured through Window > Preferences > Sigasi > (System)Verilog > Naming conventions > File header and uses
the regex syntax.
More information on file header comment checking is available here.
Report encrypted regions
Starting with Verilog 2005, regions of Verilog and SystemVerilog files
may be encrypted to protect intellectual property. Sigasi obviously
won’t check the content of these regions. Optionally, Sigasi can flag
the presence of encrypted regions in your code (rule 44). This rule is
off by default (i.e. set to IGNORE) but can be enabled (as info,
warning, or error) as required.
Multiple statements per line
For readability, each statement should be on a separate line. Sigasi
Studio will flag a warning if a line of code contains multiple
statements (rule 47).
module rule47;
reg A, B, C, D, K, M;
reg EN;
assign A = B & C, D = K & M; // multiple statements in one line: less readable
assign A = B & C; // one statement per line: more readable
assign D = K & M;
always@(*)
if(EN==1'b1) begin
A = B & C; D = K & M; // multiple statements in one line: less readable
A = B & C; // one statement per line: more readable
D = K & M;
end
endmodule
Regular expressions compatibility
Naming conventions in Sigasi
use RE2/J regular expressions.
RE2/J expressions mitigate potential performance problems that are
caused by some shapes of regular expressions using the regular Java
regular expression engine. Sigasi will warn if a naming convention
rule contains a regular expression that is incompatible with RE2/J
(rule 58).
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
1/severity/${path}={error|warning|info|ignore} # Empty loops and conditional branches
17/severity/${path}={error|warning|info|ignore} # File name does not match design unit
18/severity/${path}={error|warning|info|ignore} # File contains multiple design unit
# Verilog code line too long
20/severity/${path}={error|warning|info|ignore}
20/param/max_line_length/${path}=${integer} # at least 1
21/severity/${path}={error|warning|info|ignore} # Tabs are not allowed
22/severity/${path}={error|warning|info|ignore} # File header comment does not match required pattern
44/severity/${path}={error|warning|info|ignore} # Report encrypted regions
52/severity/${path}={error|warning|info|ignore} # Multiple statements per line
58/severity/${path}={error|warning|info|ignore} # Regular expressions compatibility
Duplicate conditions decrease readability and could lead to unused code. Duplicate conditions are often an unintended result of copy-pasting. Sigasi marks these duplicates as warnings (rule 98).
module bad_code(input clk);
if(clk && clk) begin
// Do something
end
endmodule
module good_code(input clk);
if(clk) begin
// Do something
end
endmodule
This is also the case for if-else chains or switch cases.
module bad_code(input clk);
if(clk) begin
// Do something
end else if(clk) begin
// Never called
end
typedef enum {INIT, IDLE, START, READY} t_state;
t_state state;
always @(posedge clk) begin
case (state)
IDLE : state = START;
IDLE : state = READY; // Never called
READY : state = IDLE ;
endcase
end
endmodule
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Sigasi Studio warns if a signal is assigned a value in
multiple continuous assignments (rule 101). Duplicate continuous assignments are
optimized away during synthesis. Having duplicates decreases the
readability of the code and may lead to mistakes.
module bad_sumff(input clk, rst_n, logic[31:0] d1, d2, output logic[31:0] q);
wire logic[31:0] sum = d1 + d2;
assign sum = d1 + d2;
always @(posedge clk or negedge rst_n)
if (~rst_n)
q <= 32'b0;
else
q <= sum;
assign sum = d1 + d2;
endmodule
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
In Verilog and SystemVerilog, you are not allowed to declare the same identifier multiple times within the same scope. All duplicate declarations are marked as errors (rule 95).
module bad_code;
parameter p = 0;
parameter p = 1;
endmodule
parameter p = 0;
module good_code;
parameter p = 1;
endmodule
When using the non-ANSI style, it is legal to have duplicate ports in the port list. However, such duplicate ports are often the result of a coding error and can cause unintended behavior. Duplicate ports are marked as warnings by Sigasi (rule 140).
module discouraged_code(
a,
a,
b
);
input a;
output b;
...
endmodule
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
A SystemVerilog queue or dynamic array can be initialized by using an empty assignment pattern. Though other constructs, such as structs and associative arrays, cannot be initialized this way.
module empty_assignment_pattern;
int waiting[$];
int clients[];
string names[int];
typedef struct { int fruit; } fruit_basket;
fruit_basket basket;
initial begin
waiting = '{};
clients = '{};
names = '{};
basket = '{};
end
endmodule
A SystemVerilog queue or dynamic array can be initialized by using an empty queue concatenation. Though other constructs, such as structs and associative arrays, cannot be initialized this way.
module empty_concatenations;
int waiting[$];
int clients[];
string names[int];
typedef struct { int fruit; } fruit_basket;
fruit_basket basket;
initial begin
waiting = {};
clients = {};
names = {};
basket = {};
end
endmodule
In Verilog and SystemVerilog, it is legal to have empty ports or port connections to indicate unused ports. However, this is not allowed for parameters or parameter overrides. Such errors are detected and marked by Sigasi (rules 53 and 54).
When using the non-ANSI style, it is legal to have empty ports in the port list. An empty port will be translated to an anonymous port that nullifies anything connected to it. Such empty ports are usually the result of superfluous commas and rarely reflect the intended design. Empty ports are marked as warnings by Sigasi (rule 142).
module discouraged_code(
a,
,
b
);
input a;
output b;
endmodule
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Non-blocking assignments are not allowed in functions
A non-blocking assignment (<=) is not allowed in a (System)Verilog function.
While syntactically correct, it will generally not lead to the desired behavior, and will likely cause synthesis-simulation mismatch.
Sigasi Studio flags an error if a blocking assignment is used in a function (rule 41).
A good fix to correct the problem is to replace non-blocking assignments (<=) with blocking assignments (=)
module badcode;
function plus_one;
input integer a;
begin
plus_one <= a + 1; // Incorrect: non-blocking assignment
end
endfunction
endmodule
module goodcode;
function plus_one;
input integer a;
begin
plus_one = a + 1; // Correct: blocking assignment
end
endfunction
endmodule
Function prototype has implicit return type
SystemVerilog function prototypes (pure virtual functions) should have a return type. Sigasi Studio warns for function prototypes without return type (rule 10).
virtual class badclass;
pure virtual function myfunc(input bit[31:0] data); // return type missing
endclass
virtual class goodclass;
pure virtual function integer myfunc(input bit[31:0] data);
endclass
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
41/severity/${path}={error|warning|info|ignore} # Non-blocking assignment in function
10/severity/${path}={error|warning|info|ignore} # Function prototype with implicit return type
For a class method to override a method, the corresponding method in the superclass must be virtual. If the method in the superclass is not virtual, it will be hidden instead. Hiding methods instead of overriding them is often unintentional and may indicate a missing virtual keyword (rule 132).
class Parent;
function void f();
...
endfunction
virtual function void g();
...
endfunction
endclass
class Child extends Parent;
function void f();
...
endfunction
function void g();
...
endfunction
endclass
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
The use of VHDL keywords as a (System)Verilog module name is not recommended. In mixed-language projects in particular it
could lead to unexpected results. Sigasi Studio warns when a VHDL keyword is used as a module name (rule 7).
The following naming cases should be avoided in Verilog identifiers:
module or port name ending with an underscore: bad_
any name having consecutive underscores: very__bad
The recommendation is mainly based on tool and library compatibility issues.
This is a typical unofficial convention to reserve those types of names as internal to tools.
Sigasi Studio warns for consecutive underscores (rule 42) and trailing underscores (rule 43) in module and port names.
Packed structures and unions can only contain members of packed data types and integer data types (rule 59).
class AClass; endclass
typedef struct packed { int a; } intstruct;
typedef struct packed { real a; } realstruct;
typedef struct packed { AClass a; } classstruct;
Illegal type in untagged union
Dynamic types and chandle types can not be used in untagged unions (rule 60).
class AClass; endclass
typedef union { int a; } intunion;
typedef union { string a; } stringunion;
typedef union { AClass a; } classunion;
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
7/severity/${path}={error|warning|info|ignore} # VHDL keywords as module name
42/severity/${path}={error|warning|info|ignore} # Consecutive underscores
43/severity/${path}={error|warning|info|ignore} # Trailing underscores
When a previously undeclared name is used in a port connection, a continuous assignment, or an alias, it will be implicitly declared as a scalar net of the default nettype. Such implicit declarations often arise from coding errors, such as a typo in the name or an attempt to reference something that is not available in the current scope. For this reason, all implicit net declarations will be marked as warnings.
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
In Verilog, there are two ways to declare a port list:
ANSI style: The ports are fully declared in the port list.
Non-ANSI style: The declarations of the ports are placed inside the body of the design unit.
module correct_ansi(input a, b, output c);
endmodule
module correct_non_ansi(a, b, c);
input a, b;
output c;
endmodule
When using the ANSI style, the first port of the port list must have either a direction, port type, or data type. If none of these are provided, the code is invalid (rule 135).
Although the input direction is taken by default, it is preferable to explicitly specify the direction to improve readability and make the code self-documenting.
module bad_example;
function int my_func(int a, b); // bad: direction of a and b omitted
return a+b;
endfunction
task my_task(int a, b); // bad: direction of a and b omitted
begin
$display(a);
$display(b);
end
endtask
endmodule
module good_example;
function int my_func(input int a, b); // good: direction of a and b specified
return a+b;
endfunction
task my_task(input int a, b); // good: direction of a and b specified
begin
$display(a);
$display(b);
end
endtask
endmodule
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
When choosing entity and port names in VHDL, it is recommended not to use (System)Verilog keywords.
This will prevent problems if the VHDL entity ever has to be integrated into a mixed VHDL/Verilog project.
Sigasi Studio will warn if a (System)Verilog keyword is used as an entity name.
entity always is port( -- always is a Verilog keyword: not recommended!
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
An out-of-block method declaration signature should match its prototype declaration’s signature.
Sigasi Studio flags an error if the prototype and the implementation signatures have a:
different subroutine form (task or function)
different return type, if it is a function
different arity or any argument has a:
different name
different direction
mismatched type
If an argument default value is present in an out-of-block method declaration but is missing in the prototype, or default values are not syntactically identical, a warning message is reported (rules 90, 91).
Errors are also reported for a missing prototype for out-of-bound definitions and missing or duplicated definitions for an extern method prototype.
class C;
extern task proto_only(); // missing definition
extern task who_am_i();
extern function bit bad(input int a, b, c, d, e = 2 + 3);
extern function int good(input int a, output string b);
endclass
function C::who_am_i(); // should be a task
// ...
endfunction
function C::no_proto(); // missing prototype
// ...
endfunction
function logic C::bad( // should return bit
output int a, // should be input
input integer b, // should be int
input int si, // should be 'c'
input int d = 4, // should have no default value
input int e = 5 // should be same value as prototype: 2 + 3
);
// ...
endfunction
function bit C::bad(ref x, y); // completely different signature, duplicate definition
// ...
endfunction
function int C::good(input int a, output string b);
// ...
endfunction
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
A virtual method signature should match the overridden method signature in the superclass.
Sigasi Studio flags an error if the signatures have a:
different subroutine form (task or function)
different return type, if it’s a function
different arity or any argument with a:
different name
different direction
mismatched type
If an argument default value is present in one method and is missing in the other one, an info message is reported (rule 67).
interface class A;
pure virtual task who_am_i();
pure virtual function bit bad(input int a, b, c, d);
pure virtual task too_bad(input int a, b, c, d);
pure virtual function A good(input int a, output string b);
endclass
class B implements A;
virtual function who_am_i(); // should be a task
// ...
endfunction
virtual function logic bad( // should return bit
output int a, // should be input
input integer b, // should be int
input int si, // should be 'c'
input int d = 4 // should have no default value
);
// ...
endfunction
virtual task too_bad(ref x, y); // completely different signature
// ...
endtask
virtual function B good(input int a, output string b);
// ...
endfunction
endclass
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Sigasi Studio validates the use of parameters in (System)Verilog.
Parameters without a default value
Sigasi Studio warns if a parameter is declared without a default value (rule 19). Syntactically this is allowed since the instantiating modules should provide the value to the instance parameter.
However, it is undesirable since it makes the definition dependent on a particular hierarchy and limits code reusability.
In addition, it is creating elaboration errors when attempting to use such modules as a top-level.
The Verilog standard does not allow empty parameter overrides (rule 54).
module test;
sub#(8, 16, ) inst(); // dangling comma is not allowed
endmodule
module test;
sub#(8, 16) inst();
endmodule
Local parameter has to be initialized
The Verilog standard requires that local parameters are initialized (rule 69).
localparam p; // initialization missing
localparam p = 1;
Local parameter cannot be overridden
The Verilog standard does not allow the overriding of local parameters (rule 70).
module name(
input clk,
input rst
);
localparam int test = 42;
defparam test = 0; // override not allowed
endmodule : name
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
19/severity/${path}={error|warning|info|ignore} # parameter without default value
48/severity/${path}={error|warning|info|ignore} # parameter width mismatch
53/severity/${path}={error|warning|info|ignore} # empty parameter
54/severity/${path}={error|warning|info|ignore} # empty parameter override
69/severity/${path}={error|warning|info|ignore} # local parameter not initialized
70/severity/${path}={error|warning|info|ignore} # local parameter overridden
Sigasi Studio has several checks on Verilog port and parameter associations.
Named parameter and port connections have to be used for all instances with many parameters / ports
A long list of positional parameters or port connections is difficult to read and maintain. Therefore, Sigasi Studio warns if a
list of positional connections is longer than 3 items (rules 24 and 26). If the number of associations is larger than 3, named connections should be used.
module sub(input clk, arst, enable, data, output reg data_out);
always @(posedge clk or negedge arst)
if (~arst)
data_out <= 1'b0;
else if (enable)
data_out <= data;
endmodule
module badtop;
logic clk, arst, en, a, b;
sub sub_inst(clk, arst, en, a, b); // 5 ordered associations: difficult to read and maintain
endmodule
module goodtop;
logic clk, arst, en, a, b;
sub sub_instance (
.clk(clk),
.arst(arst),
.enable(enable),
.data(a),
.data_out(b)
);
endmodule
Named and positional associations cannot be mixed
Sigasi Studio flags an error when attempting to mix named and positional port or parameter associations (rule 25).
module sub#(PARAM_1=2, PARAM_2=3) ();
endmodule
module badtop;
// Syntax error: mix of named (`PARAM_1`) and positional (`3`) association
sub#(.PARAM_1(2), 3) sub_inst();
endmodule
module ok_top;
// All associations are positional: OK but harder to understand and maintain
sub#(2, 3) sub_inst();
endmodule
module goodtop;
// All associations are named: best practice
sub#(.PARAM_1(2), .PARAM_2(3)) sub_inst();
endmodule
Unresolved formal names
Sigasi Studio flags an error for named port and parameter connections if the instantiated module doesn’t have ports with these names.
Sigasi Studio flags an error for duplicate named port and parameter connections (rule 37).
module sub#(WIDTH=8) (input[WIDTH-1:0] i1=1'b0, i2, output[WIDTH-1:0] o1);
endmodule
module badtop;
logic a, b, c;
// parameter `WIDTH` and port `i1` are connected twice
sub#(.WIDTH(4), .WIDTH(6)) sub_inst(
.i1(a),
.i1(b),
.o1(c)
);
endmodule
module goodtop;
logic a, b, c;
// parameter `WIDTH` and port `i1` are connected once
sub#(.WIDTH(4)) sub_inst(
.i1(a),
.o1(c)
);
endmodule
Missing actuals for formals that have no default value
Sigasi Studio warns about missing port or parameter connections if the ports or parameters don’t have a default value (rule 38).
module sub
#(LHS, RHS=0)
(input[LHS:RHS] i1=1'b0, i2, output[LHS:RHS] o1);
endmodule
module badtop;
logic[7:0] x;
// parameter `LHS` and port `i2` don't have a default value so they must be connected
sub sub_inst(.o1(x));
endmodule
module goodtop;
logic[7:0] x;
wire[7:0] y;
sub#(.LHS(7)) sub_inst(
.i2(y),
.o1(x)
);
endmodule
Excessive number of actuals in ordered notation
Sigasi Studio flags an error if the number of positional parameters or port connections is larger than the number of parameters or ports of the instantiated module (rule 39).
module sub#(WIDTH=8) (input[WIDTH-1:0] i1=1'b0, i2, output[WIDTH-1:0] o1);
endmodule
module badtop;
logic a, b, c, d;
// Expecting 1 parameter connection and 3 port connections instead of 2 and 4
sub#(4, 6) sub_inst(a, b, c, d);
endmodule
module goodtop;
logic a, b, c;
sub#(4) sub_inst(a, b, c);
endmodule
Note that if there are too few positional parameters or port connections, an error for missing connections will be flagged.
Named connections are not allowed with blank ports
If an instantiated module contains a null port, the instantiation must use port association by order and not by name (rule 56).
module sub(
input clk,
, // this is a *null port*
input rst
);
endmodule
module badtop;
sub sub_instance(
.clk(clk),
.rst(rst)
);
endmodule
module goodtop1;
sub sub_instance(
,clk,rst
);
endmodule
module goodtop2;
sub sub_instance(
clk,foo,rst
);
endmodule
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
# Whitespace following a backtick
24/severity/${path}={error|warning|info|ignore}
24/param/max_ordered_port_connections/${path}=${integer}
# Invalid preprocessor syntax
26/severity/${path}={error|warning|info|ignore}
26/param/max_ordered_parameter_overrides/${path}=${integer}
Verilog and SystemVerilog always constructs without an event control statement at the top cannot be synthesized.
Additionally, they would activate in random order at the moment 0 at the beginning of a simulation.
Sigasi Studio warns about always blocks without an event control statement at the start.
A good way to correct this description is to place the timing control statement at the top.
module test(clk, data_in, data_out);
input clk;
input[3:0] data_in;
output reg[3:0] data_out;
always
begin
data_out <= data_in;
@(posedge clk); // Timing control not at the top of 'always'
end
endmodule
module test(clk, data_in, data_out);
input clk;
input[3:0] data_in;
output reg[3:0] data_out;
always @(posedge clk)
data_out <= data_in;
endmodule
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Expression Type Requirements in Different Contexts
In Verilog and SystemVerilog there are dozens of places where an expression or identifier of a specific type is required, e.g., operators have expectations on operand types, there are limitations on what a class can extend or implement, etc. It may not be obvious at first glance if a variable or net type complies with these requirements. Such non-compliances will be detected and marked by Sigasi (rules 78, 79, 100 and 131).
Extending and Implementing
Interface classes can only extend other interface classes, while classes can only extend classes and only implement interface classes:
class Foo;
endclass
interface class Bar extends Foo; // Expected interface class but got 'class Foo'
endclass
class Baz
extends Bar // Expected class but got 'interface class Bar'
implements Foo; // Expected interface class but got 'class Foo'
endclass
Types vs Value Expressions
While let declarations are advertised as a replacement to preprocessor macros and they can have untyped arguments, you still cannot pass types as arguments (unlike selected system functions):
module test;
let my_typename(expr) = {$typename(expr), "!"};
initial $display(
"my: %s\nsys: %s",
my_typename(int), // Expected value expression but got type: int
$typename(int)
);
endmodule
Operand Data Types
Unary logical reduction operators expect integral operands:
function logic parity(input real data);
parity = ^data; // Expected integral expression but got 'real'
parity = ^$realtobits(data);
endfunction
Bit-stream Types
You can unpack a stream of bits into an unpacked struct if all its fields are of bit-stream types. Here, one of the struct fields is shortreal which makes the whole struct non-streamable:
package pkg;
typedef struct {
shortreal data; // shortreal is not a bit-stream type
logic [6:0] unused;
logic parity;
} real_payload;
endpackage
module test (logic [39:0] data);
pkg::real_payload payload;
assign {>>{payload}} = data; // Expected bit-stream data expression but got 'struct pkg::real_payload'
endmodule
These are but a few examples. Sigasi Studio checks numerous other expression expectations in different contexts in SystemVerilog, immediately showing incorrect types and variables usages.
Type Compatibility
Verilog and SystemVerilog’s type compatibility rules can be obscure, especially considering implicit type conversion and complex expression evaluation rules. To help you avoid any pitfalls, the type checker ensures that assigning ports, nets, or variables is done safely.
Here are a few examples where Sigasi Studio would report an error:
Unions and Structs
Even though these two unions and structs have the same signature, they implicitly define two anonymous types; they are thus not assignment compatible.
String Variables and Literals
string variables and literals behave differently.
null cannot be assigned to string variables.
String variables cannot be assigned to int variables because they are dynamically sized ordered collections of characters that are not assignment compatible to int.
However, string literals can be used to initialize ints as they are treated as unsigned integer constants.
Syntax Confusion and Implicit Casting
The concatenation and assignment pattern syntax confusingly resemble each other a lot.
It is not always clear what assignments will be implicitly cast. enums are implicitly cast to ints, but not the other way around.
Classes
Subclasses can be assigned to superclasses, but not vice-versa. Every Apple is a fruit, but not every Fruit is an Apple. Similarly, classes unrelated to one another (Fruit and Vegetable) are not assignment compatible.
Ref Ports
The type of the actual value should be equivalent to the formal ref port type (rule 94).
module test;
task automatic inc(ref [3:0] value, input [3:0] amount);
value += amount;
endtask
bit [3:0] value = 10;
initial begin
// Expected expression type to be equivalent to target type 'logic [3:0]' but got 'bit [3:0]'
inc(value, 5);
$display(value);
end
endmodule
A declaration that is never used does not contribute anything to a design and can be an indication of a coding error. Unused declarations will be marked as warnings.
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
When talking about hierarchy, references can be divided into three groups:
Downward references, starting from current module items;
Hierarchical references, starting from the top level; and
Upward references, starting from some module in between the top level and the current module.
Upward references can make the code very hard to understand, and hence to debug and maintain, so Sigasi warns you against their usage (rule 99).
module top(input i1, i2, output o1, o2);
mid mid1_inst(.i(i1), .o(o1));
mid mid2_inst(.i(i2), .o(o2));
endmodule
module mid(input i, output o);
int x;
assign x <= 3 * i;
assign o <= 3 * x;
bottom bottom_inst();
endmodule
module bottom();
initial $display(mid.x); // whichever mid's x could it be?
endmodule
Rule configuration
This rule can be disabled for your project, or its severity
and parameters can be modified in the project linting
settings.
Alternatively, it can be manually configured with the following template:
Sigasi Studio has a number of checks on VHDL coding style.
Extended identifier contains whitespace
Sigasi Studio flags an info message when using extended identifiers
that contain whitespace. Particularly in mixed-language
designs, these identifiers may cause problems in
Verilog and SystemVerilog as they use whitespace to mark the end of
an extended identifier.
signal \foo bar\ : std_logic -- identifier with spaces: not recommended!
Line is too Long
For legibility, it is recommended to keep lines of code short. Sigasi Studio warns if a code line is longer
than a certain length. The maximum length is set to 120 characters by default, but this can be configured on
the Errors/warnings page of the project settings or workspace preferences.
Magic number, bitstring, or string in statement
A design often requires certain constant numbers, bitstrings, or string literals. To optimize code maintainability, it is recommended to use generics or define such literals in constants rather than hardcoding them directly into statements. If this rule is enabled, Sigasi Studio will flag all magic numbers, bitstrings, and strings used in statements.
The rule can be configured to work on numbers, bitstrings, and/or strings. It is also possible to configure a set of literal values that are allowed in statements, this is done using a regular expression.
When writing an expression containing a sequence of operators the order of execution might not always be obvious. For this reason, it is recommended to add sufficient parentheses to expressions that include multiple non-associative operators. If this rule is enabled, Sigasi Studio will flag all such expressions.
s_output <= s_input mod 4 + 3;
s_output <= (s_input mod 4) + 3;
Constant width vector assigned to signal
To optimize code maintainability and portability, it is not recommended to assign vectors of constant width to signals. If this rule is enabled, Sigasi Studio will flag all signal assignments that use constant width vector literals.
s_output <= "00000000";
s_output <= (others => '0');
Rule configuration
These rules can be disabled for your project, or their severity
and parameters can be modified in the project linting
settings.
Alternatively, they can be manually configured with the following template:
# Extended identifier contains whitespace
228/severity/${path}={error|warning|info|ignore}
# Line is too long
97/severity/${path}={error|warning|info|ignore}
97/param/max_line_length/${path}=${integer} # at least 1
# Magic number, bitstring, or string
235/severity/${path}={error|warning|info|ignore}
235/param/check_number/${path}={true|false}
235/param/check_bitstring/${path}={true|false}
235/param/check_string/${path}={true|false}
235/param/allow_literal_pattern/${path}=${regex}
# Sequence of operators without parentheses
230/severity/${path}={error|warning|info|ignore}
# Constant width vector assigned to signal
231/severity/${path}={error|warning|info|ignore}
Sigasi Studio flags an error if a mismatch exists between the selected
VHDL language versions of a project, VHDL common libraries,
and individual design files (rule 170).
Applying the associated quick fix will upgrade the version of the project,
or - if it’s already set up correctly - it’ll upgrade the version of the file with the outdated version.
The Common Libraries will automatically be updated to the upgraded version.
In Sigasi Studio, you can set the version of the VHDL
language for
your project and individual files. The setting for individual
files is only intended for compatibility with legacy code. Setting a
higher VHDL version on a design file than the VHDL version of the
project is not supported and will cause this error to appear.
Sigasi Studio is distributed online. It is available in two versions: as a
stand-alone application or as a plugin inside a standard Eclipse
installation. Your license gives you the right to use either version, at
any time, at your discretion. Therefore, your first task is to decide
which version suits your requirements, based on the description below.
Depending on the chosen version, you should then follow the
corresponding installation instructions.
Sigasi Studio App
The stand-alone application has the following characteristics:
Recommended if you are not using Eclipse yet
Installation is trivial: just unzip!
Everything is included in a single download
Well-balanced set of features
Optimized for VHDL and Verilog development
Complete freedom to add and configure plugins
Sigasi Studio Eclipse Plugin
The Eclipse plugin has the following characteristics:
Can be useful if you are using Eclipse already
Easily plugged into your existing Eclipse platform
Complete freedom to add and configure plugins
Over one thousand other Eclipse plugins to choose from
Support for C, C++, Tcl, and other languages
Support for many version control systems
When updating an existing installation, you need to extra care to diasble the
option Contact all update sites during install to find required software.
Not doing so might break your installation.
Sigasi Studio Custom Installation
Recommended for (larger) teams
Automates the setup of Eclipse, the Sigasi Studio plugin, and your project
Ensure that team members have a uniform setup
Quickly set up Eclipse with Sigasi Studio
Configure team preferences during setup
Check out a project from version control at setup time
Optionally add support for other programming languages
To download and install Sigasi Studio as a stand-alone application, follow the
online Installation Instructions.
After downloading, choose or create a folder where you want to install
the software and unpack the archive there. The archive contains a
single top-level folder called sigasi. Inside the folder, there is an
application startup file, also called sigasi. Start the application by
executing this startup file.
If you are using RedHat Linux 6 or CentOS 6, you need to follow the Plugin installation
instructions as explained here.
Running Sigasi Studio with multiple users on the same server
The following section is only relevant if you’re using a Sigasi Studio version older than Sigasi Studio 4.17.2.
Starting with Sigasi Studio 3.8, the Sigasi launcher listens on port 4444. To avoid conflicts on this port when Sigasi Studio is used on a server with multiple users concurrently, the following changes need to be made:
Edit sigasi/configuration/config.ini and replace eclipse.application=com.sigasi.runner.open with eclipse.application=org.eclipse.ui.ide.workbench
In sigasi/sigasi.ini add following lines between @noDefault and -vmargs:
--launcher.defaultAction
openFile
If there are other arguments between @noDefault and -vmargs, append to these.
This way Sigasi Studio uses the default Eclipse behavior instead of the custom Sigasi runner.
More information on the Eclipse OpenFileFeature can be found here.
The Sigasi runner allows you to open projects using the -p option.
This is not possible when using the default Eclipse runner.
Installation of Sigasi Studio Eclipse Plugin
There are two ways to install the Sigasi Studio Eclipse Plugin:
You can check your Java version with java -version
Java can be downloaded from several sources, a.o. Adoptium.
Prerequisites: Eclipse
You need to have at least Eclipse version 2021-03 (4.19).
This Eclipse version and the Sigasi Studio plugin require Java 11 or 17.
If you don’t have Eclipse installed yet, the C/C++ flavor would be a good place to start. Just download (Windows 64 bit/Linux 64 bit/Other versions), unzip, and start.
This requires the host where you install the Sigasi Studio Plugin to have access to our download server.
After starting Eclipse:
Click Help > Install New Software….
In the Work with: field enter https://download.sigasi.com/sigasi-studio/updates/studio and press enter.
Check the checkbox next to Sigasi Studio.
Since Sigasi Studio 4.15, installing Sigasi Studio optional features is no longer recommended.
You must disable the option Contact all update sites during install to find required software when installing the plugin.
Click the Next button.
The following steps are pretty self-explaining.
After the installation, you will need to restart Eclipse. Once this is done, go to Window > Perspective > Open Perspective > Other… and select the Sigasi Perspective. You can then close the Welcome View to show the Sigasi Views.
Installing the Offline Update Site
Installing the offline update site is very similar to installing from the main update site, where step 2 is replaced with these steps:
Download the offline update site
In the Install Wizard, click Add…
Click Archive…, browse to the zip file you downloaded, and confirm with OK.
Next, continue with step 3. in the general eclipse installation instructions.
It is recommended to disable the option Contact all update sites during install to find required software
when installing update sites.
GPG Certificate Validation
Eclipse 4.26 (2022-12) added GPG certificate checking capabilities. When you install new plugins, you will be prompted to trust any not-yet-trusted GPG keys or unsigned artifacts. Because Sigasi artifacts are correctly signed using GPG, you can expect to see the following screen the first time you install or update Sigasi in an Eclipse >= 4.26.
Previously trusted keys can be inspected by going to Window > Preferences > Install/Update > Trust.
You can refer to this page for all information regarding GPG at Sigasi.
Licensing
The license key can be filled in under Window > Preferences > Sigasi > License Key.
More details can be found here. The license unlocks the features for your edition.
Configuration
Sigasi Studio stores its projects on the file system in one or more
workspaces.
When you start the tool for the first time, it will propose to create a
workspace for you:
Although you can work with multiple workspaces, we recommend using a
single workspace for all your projects.
Software Updates
Sigasi Studio has an automated update system. When updates are available, you
are notified by a pop-up window called Updates Available in the
bottom right corner:
If you want to install the updates, click anywhere in the pop-up window.
After a few seconds, a new window will appear with further instructions.
The updates can be postponed by closing the pop-up. You can perform the
updates at any time by clicking the
-icon in the status bar
at the bottom of the screen.
It is good practice to first create a backup of your installation folder before running an update. This can be done by simply compressing the eclipse or the sigasi folder in an archive (zip file)
Update Sigasi Studio App
If you run Sigasi Studio as a standalone application, the automated update system will periodically check for software updates.
Update Sigasi Studio Eclipse plugin
If you run Sigasi Studio as an Eclipse plugin, you may need to check for updates manually, by clicking Help > Check for Updates.
You can enable automatic updates by opening this preference page: Install/Update > Automatic Updates. Next, enable Automatically find new updates and notify me. Feel free to modify any of the available options.
Firewalls and Proxies
If the updates are not automatically fetched from the Sigasi Studio update server you are probably behind a firewall or proxy server. You can configure Sigasi Studio’s proxy settings in Window > Preferences > General > Network connections.
Make sure to set the Active Provider to Manual and configure the appropriate Proxy entries.
Whether you need to configure the entries for HTTP or HTTPS depends on the Locations configured in the Available Software Sites settings.
If you can not add a firewall exception for our update site, the fallback solution is to download the complete application from our website.
You can completely replace your old installation; all settings are stored in your workspace (the default is workspaceSigasi in your home directory).
Your work with Sigasi Studio is typically organized as a project. A project
is a collection of VHDL and/or Verilog/SystemVerilog files that belong together. Sigasi Studio
understands the HDL units defined in the files and the relationships between them.
Your first step is to set up a project. There are several ways to do this.
The most common ways are:
Note that while you initially need to choose between a VHDL and a Verilog/SystemVerilog project, any Sigasi Studio project can be a mixed language project.
If you wish to create a mixed language project, we recommend importing or creating a VHDL project and then adding the Verilog/SystemVerilog support to this project.
To create a mixed language project, right-click your project and select Configure > Add VHDL Support or Configure > Add Verilog/SystemVerilog Support as needed.
Features
In projects, you can navigate from instantiation statements to the matching entity or module.
This also works in mixed language projects.
You can navigate from VHDL entity instantiations in Verilog/SystemVerilog code and to Verilog/SystemVerilog module instantiations from VHDL code.
You can also open the declaration of ports and generics/parameters in mixed instantiations.
Other supported features:
Find references for entity names, modules, ports, generics, and parameters.
Autocomplete Verilog/SystemVerilog module instantiations in VHDL code and VHDL entity instantiations in Verilog/SystemVerilog code.
Error reporting of incorrect entity names, modules, ports, generics, and parameters in instantiations.
You can import an existing VHDL or Verilog/SystemVerilog project from the file system by clicking
File > Import… > Sigasi > Import a VHDL project or Import a (System)Verilog project. Browse to the
root directory of the project, and press Finish.
2: Set Libraries (VHDL or Mixed)
Since Sigasi Studio 4.4, Sigasi Studio automatically configures libraries of imported projects, based on project information
such as library and use clauses. If you need to customize the library configuration, you can assign different
libraries to your files and folders. Right-click on a file or folder and select Library Mapping > New Library….
Then fill out the correct library name.
If you need additional files that are not in the project root directory,
just drag them from your file browser into the project. You will have
the option to create a link rather than copying the files.
Note 1: dragging files works on Windows (using Windows Explorer), and
on Linux (using Gnome Nautilus). If you use KDE, you should install Nautilus.
Note 2: to avoid absolute paths in the .project file, environment variables can be used.
Right-click the file or directory in the project explorer and select
Properties > Resource > Location > Edit… to configure the path of the resource.
To access environment variables, you have to prefix the environment variable with ENV-.
For example: to refer to the home directory you can use ENV-HOME.
Creating a new, empty project
To create a new project, select File > New > VHDL Project or
File > New > Verilog Project. Then give your project a name.
By default, the Use default location checkbox is checked, which
means that new projects will be located in the workspace folder.
Alternatively, you can uncheck the checkbox and choose an arbitrary
location for your project. This is especially useful if you want to use
Sigasi Studio with an existing design.
You can also select the VHDL version or the version of .v files.
After creating a new project, you can add existing files by dragging
them from your filesystem into the project explorer. New files can be
added by clicking File > New > VHDL File, File > New > Verilog File,
or File > New > SystemVerilog File.
Other ways to set up a project
Adding VHDL or Verilog/SystemVerilog support to an existing Eclipse project
You can also add VHDL or Verilog/SystemVerilog support to any project in your
workspace by right-clicking the project in the project explorer and
selecting Configure > Add VHDL support or Configure > Add
Verilog/SystemVerilog Support. You can also remove VHDL or Verilog/SystemVerilog
support from Sigasi Studio projects by selecting Configure > Remove VHDL Support
or Configure > Remove Verilog/SystemVerilog support.
Note that with a Sigasi Studio XL
or a Sigasi Studio XPRT
license, you can have mixed VHDL and
Verilog/SystemVerilog support at the same time.
Importing a project from an archive
Sigasi Studio projects can be shared using file archives. All project-related
settings are stored in two hidden files in the project folder.
Therefore, you can create an archive of the entire top level folder
(File > Export > General > Archive file) and send it to someone
else.
You can import a project from an archive by clicking
File > Import…> General > Existing Projects into Workspace
and selecting Select archive file. Browse to your project archive
and press Finish.
Programmatically creating a project
The Sigasi Studio .project and .library_mapping.xml files can be created using code from our
publicly available Sigasi Project Creator project.
The project offers Python classes that make it easy to generate a Sigasi Project from your own project
specifications.
For more information and examples, check out the Sigasi Project Creator project on GitHub.
Deprecated Features
Note that resource filters are discouraged in Sigasi Studio for Eclipse and unsupported in
Sigasi Studio for VS Code and Veresta.
HDL libraries are a very powerful feature of the HDL languages. Sigasi Studio
makes it easy to configure and use them. In this chapter, we assume that
the basic concepts of HDL libraries are understood. We will explain how
they are implemented in Sigasi Studio.
Like with any HDL tool, Sigasi Studio needs to know where the libraries are
located on the file system. We will describe how the library
configuration can be examined and modified using the GUI.
We will also present some use case about how to set up libraries with
Sigasi Studio to organize your projects.
Examining the library configuration
You can examine the library configuration in the Libraries View
and in the Project Explorer view. The Libraries view shows how
design units are mapped. The Project Explorer view show how VHDL or
SystemVerilog files are mapped.
In the Libraries view you can see a tree of all libraries in your
projects. You can open each library to see all contained design units as well as their description style.
In the Project Explorer view each physical file or folder is annotated
with the library it belongs to, between square brackets:
What you see here is the initial library mapping of a demo project (you
can create such a project by selecting File > New > Other > Tutorial
VHDL Project or Tutorial SystemVerilog Project).
In the screenshot we see a project called Demo, with a folder named
Common Libraries. In that folder, you see the typical standard
libraries (std and ieee) upon which all VHDL projects depend. The
demo project itself consists of a few VHDL files.
Next to the project’s name Demo, is the annotation work. This means
that, barring any overrides, everything in the project will be stored
inside the work library.
Lower down, we see overrides. For example, the STD folder has an
annotation std. This means that, again barring any further overrides,
the entire contents of the STD folder will be mapped into the library
std. There are no limits to the number of overrides that can be
performed. If this needed, any individual file can be mapped to a
separate library.
Modifying the library configuration
The library mapping for project files can be modified in the Libraries
and Project Explorer view.
Select a file or a folder in the Project Explorer and right-click.
You get a Set Library context menu, with a number of options:
Select Exclude from build to exclude the file or folder from any library
Select New Library… to define a new library and map the file or folder to it
If one ore more folders are selected, the folder can be added to a library with the folder name(s)
Select the name of an existing library to map the file or folder to that library
When you map a file into a library, only that file is affected. However,
when you map a folder into a library, then everything in that folder
will be mapped into that library. Any overrides in the folder and its
sub-folders will be removed. When you are defining the library mapping
for a new project you should map from top to bottom.
So in the case of our Demo project, you would change (if work is not
a good default) the top folder’s mapping first and then override the
mapping in the sub-folders.
When you are changing the library mapping of a project, the project will
be rebuilt completely. In order to avoid several consecutive rebuilds
while you are setting up your libraries, you can temporarily disable the
automatic rebuilds, until you are finished setting up your library
mappings. You can do this by disabling the Project > Build
Automatically option.
To exclude a file from all libraries, the library mapping context menu
provides an Exclude from build option. You can apply that to any file or folder in
the project. Sigasi Studio will then assume that the corresponding resource is
not a part of the project and will not include that resource in a
project build. This is typically useful when you have stale copies of
HDL files or folders lying around that you want simply to be ignored.
(System)Verilog include files
(System)Verilog include files are always excluded from the build. Any
file that is included in another design file gets excluded from the
build, even if it has an extension that would normally identify it as
a design file, e.g. .v or .sv. It often doesn’t make sense to
compile include files by themselves. Instead, include files are
compiled in the context of the file in which they are included.
Configuration file
All library configuration information is stored in the .library_mapping.xml
file in the root of your project.
If you edit this file, your project will be cleared and rebuilt automatically
(a so-called Clean Build).
Sigasi Studio only writes changes to this configuration file when you make
changes to the library configuration with the context menu in the
Project Explorer.
When you do make changes, Sigasi Studio first checks that all paths in the
library configuration still exist. If a path no longer exists, it will be
removed from the configuration file.
Note that the library configuration file is case-sensitive, even on Windows.
Library configuration warnings and Quick Fix
If the library mapping file contains invalid entries, there will be a warning on the .library_mapping.xml file.
This warning will show in the Project Explorer, in the editor and in the Problems View.
An associated Quick Fix is available through the Problems View.
When invoked, it will remove all invalid entries from the .library_mapping.xml file.
Common Libraries
Each project has a folder called Common Libraries.
This is where reusable libraries go: either vendor libraries, third party IP
libraries or your own reusable libraries. By default, the STD and IEEE
libraries are added to this folder.
The Common Libraries folder behaves like any other folder.
You can delete it, rename it and apply a different library mapping.
In most cases, however, the default configuration is just what you need.
If your project doesn’t have a Common Libraries folder, you can just
create it by right-clicking the project in the Project Explorer and
selecting the New > Folder dialog. In the New Folder dialog,
select Advanced and Virtual Folder and name the folder Common Libraries.
How to add files to Common Libraries?
In any newly created VHDL project, the Common Libraries folder
contains the VHDL files of the IEEE and STD libraries.
To add files to the Common Libraries folder, locate a folder with VHDL files
on your file system using the Project Explorer or the file explorer of your OS
and drag the folder with VHDL files to the Common Libraries folder.
Alternatively, you can right-click the Common Libraries folder and select the
New > Folder dialog where you can use the Advanced » settings to create
a Linked Folder pointing to the actual folder location that contains the
files you wish to add to the Common Libraries.
How is Common Libraries different from another folder?
Common Libraries by default is a virtual folder. This means that it is not
a real folder in the project directory and it can only contain references to
folders on your file system.
Files in Common Libraries are supposed to be error free. Sigasi Studio
will not mark errors or warnings in these files.
Next to these, a few other libraries’ errors and warnings are never marked, regardless of their location.
These libraries are: std, ieee, altera_mf, altera, XilinxCoreLib, unisim, mentor, lpm, simprim, std_developerskit, unimacro, and modelsim_lib.
While you work on your project, you don’t want to edit the files in the
Common Libraries, but you need them to compile your project.
If you activate an external compiler,
files in Common Libraries are supposed to be pre-compiled. If you tell
Sigasi Studio to compile your project using an external compiler, the
Common Libraries are skipped. You need to pre-compile them yourself and let
your compiler know where the compiled libraries are. For ModelSim, you can
use the “modelsim.ini” file for this. If your project root contains a “modelsim.ini”
file, it will be used instead of the default “modelsim.ini” file.
Pre-compile Common Libraries
This section links to various recommendations on to pre-compiling the simulation models of external libraries in the Common Libraries, depending on the external compiler.
You don’t need to pre-compile VUnit libraries for running
VUnit tests. The VUnit framework compiles its own library when needed.
If you’re using libraries like OSVVM, you need to call
add_osvvm() in run.py to tell VUnit to also compile the OSVVM
library.
Further documentation on using VUnit in Sigasi Studio is available
here.
External compiler in a VUnit project
If you want to configure an external compiler in a VUnit project
(e.g. for additional syntax checking), you need to ensure that the
compiler has the VUnit library. Otherwise, the compiler will flag all
VUnit constructs in your HDL code as errors.
This script
demonstrates how to compile and enable the VUnit library for Modelsim
and Questa. Run this script in the folder where you want to install
the compiled VUnit library. This should be outside your project
folder. The script takes the path of your VUnit installation as a
parameter. Once the compilation is finished, go to your project
folder and run these commands:
vmap -c # only if your project folder doesn't contain modelsim.ini alreadyvmap <folder_where_the_script_ran>/vunit_lib vunit_lib
Note that the OSVVM library is shipped with Modelsim, so you won’t
need to compile it yourself.
For other external compilers, a similar approach is needed. Customers
who need help with that are welcome to contact
support.
What if I broke my Common Libraries folder?
If you have modified the Common Libraries folder, you can always
revert it back to the original state.
Right-click on the Common Libraries folder of your project in the explorer
view and apply menu-entry Set Library > Reset Common Libraries.
Resetting the library mapping
Sigasi Studio contains two functions to reset all or part of the library mapping.
Reset Common Libraries updates the common VHDL libraries to the
version (‘93, ‘2002, ‘2008, ‘2019) required by your
project. User-defined common libraries remain untouched. To
access this function, right-click the Common Libraries folder
inside your project in the Project Explorer and select Set
Library > Reset Common Libraries.
Reset Library Mapping resets the entire library mapping of your
project. After resetting the library mapping, Common Libraries
are reset as above, and all design files are mapped to library
work. Note that this action cannot be undone, so only use it
when you want to rebuild the library mapping from scratch. To
access this function, right-click your project in the Project
Explorer and select Set Library > Reset Library Mapping.
Sigasi Studio allows you to share libraries between multiple projects. The
easiest way to do this, is to develop each library in a separate project
and configure the Project Dependencies accordingly. To configure the
project dependencies, right click the project (the one that uses the
shared library) and select Properties. Next click Project
References and mark the library project as referenced project.
Using third party libraries
Many projects use third party libraries. These can be added to the
project as any other set of VHDL files.
A number of popular third party libraries are the following:
Vendor
Library
Install dir example
AMD/Xilinx
unisim
C:\Xilinx\Vivado\2020.1\data\vhdl\src\unisims
AMD/Xilinx
unimacro
C:\Xilinx\Vivado\2020.1\data\vhdl\src\unimacro
AMD/Xilinx
XilinxCoreLib
C:\Xilinx\14.4\ISE_DS\ISE\vhdl\src\XilinxCoreLib
AMD/Xilinx
xpm
C:\Xilinx\Vivado\2020.1\data\ip\xpm
Intel
altera_mf
C:\Intel\17.0\quartus\libraries\vhdl
Mentor
modelsim_lib
${ModelSimPath}\vhdl_src\modelsim_lib
Aldec
aldec
C:\Aldec\Riviera-PRO-2015.02\vlib\aldec\
On Linux the default installation location for AMD/Xilinx software is /opt/Xilinx.
XilinxCoreLib is a very big library with more than a thousand entities and
architectures. If you include all of these design units, it slows down the
compilation phase of Sigasi Studio. In order to avoid that, Sigasi Studio
only adds the packages with the component declarations to your project by
default. It excludes the entities and architectures from compilation.
You can easily add selected entities (and architectures) to your project by
right clicking the corresponding file (filename = entity name.vhd) in the
Project Explorer, and selecting
Set Library > xilinxcorelib.
Library errors from external compilers
If you are using the External Compilers, the external compiler
can also put error markers on library clauses. You can easily verify this by
checking the prefix of the error message (e.g. vcom: for vcom errors).
Consult the Libraries section of the external compiler
integration for more information on configuring libraries for your external
compiler.
Sigasi Studio is built upon the Eclipse platform, which permits to use multiple languages within a single environment. The user interface can be customized for a particular language. In Eclipse terminology, this customized user interface is called a perspective. The icon and name of the current perspective is highlighted in the upper right corner.
Sigasi Studio provides a Sigasi perspective to work with both VHDL and Verilog files.
If you use the standalone version of Sigasi Studio, this perspective is the default. If you use the Eclipse plugin, another perspective may be open instead. You can select the Sigasi perspective by clicking the button next the perspective icon. A window pops up in which you can select the perspective.
You can right-click the perspective button to customize toolbar contents, to reset the perspective to its default layout or to save your own, customized perspective.
Quick Access
The Sigasi Studio toolbar contains a widget called Quick Access. This widget allows you to quickly find open editors, available perspectives, views, preferences, wizards, commands, etc. Simply start typing the name of the item you wish to invoke.
When you open a project in Sigasi Studio, a number of views are presented
in the user interface. Here is a typical screenshot, with the views
highlighted.
The views provide alternative ways to access the information in a
project. They permit efficient navigation, inspection, and editing.
This chapter lists and explains the most important views of Sigasi Studio. Some views are not covered here, more specifically some views that are either inherited from Eclipse, or views that are provided by third-party plugins. Please refer to the Eclipse documentation or the specific plugin documentation for further information on those views.
Via Window > Show View. If the view is not in the visible list, choose Other… and select the view in the selection dialog.
By right-clicking in the editor and selecting Show in > ….
Some views also support opening the current selection (e.g. the Block Diagram View). This selects the element in the view that corresponds to the current selection in the editor.
Project Explorer View
This view shows the directory structure of all files in all projects.
You can use it to navigate to a particular file in your project and
select it. When you double-click on a file, the file opens in the Editor
view. If you right-click a file, you see the context menu which offers
extra commands.
You can customize the behavior of the Project Explorer View in ways
that can be particularly handy for large projects. For example, if you
click the Link with Editor icon
, the Project Explorer
will be linked to the Editor view. Now, the active file in the editor
view will always be selected in the Project Explorer.
You can apply filters to choose which files are shown. Select the icon
View Menu and then
Customize view. You can then select a filter whose matching files
will be hidden in the view. For example, you can filter out all non-VHDL
or non-Verilog files.
The Project Explorer View provides textual and graphical Label Decorations which can be controlled
in Window > Preferences > General > Appearance > Label Decorations.
Label decorators are a visual guide on the state of projects, folders, and files.
Decorators can depend on various plugins.
The following descriptions apply to Sigasi-specific decorators.
Sigasi Studio adds text decorators to the right to indicate which library a project, file, or folder is mapped in. The library name is denoted in square brackets.
If a project is in a different folder than the workspace, this is denoted within round brackets.
Other text decorators to the right of a project are probably from the Git plugin. The repository name and branch are denoted with square brackets.
Open HDL projects have a bridge-like overlay in the top right corner of the project icon.
File icons with a ‘V’ in them are VHDL or SystemVerilog source files.
Folder icons with an overlay in the lower right corner are virtual folders (white square) or linked folders (square with arrow).
Other overlays in the lower right corner are probably from the Git plugin. They indicate tracked files/folders (yellow cylinder) and non-tracked files/folders (question mark). Changed files are noted with a > mark next to the icon.
Overlays in the lower left corner are generally indicating status from Sigasi Studio: errors in files/folders are indicated with a red square and white cross while files/folders with warnings are marked with a yellow triangle with black exclamation mark .
If you exclude a file from build in Sigasi studio, the icon will be overlayed with a red forbidden entry icon in the upper left corner.
Editor View
The Editor View shows the content of files and allows you to edit
files. It is a tabbed view so that multiple files can be opened for
editing simultaneously. The currently selected file is the active file.
The Outline View displays the contents of the active file, in terms of
the HDL objects that it contains.
You can sort the elements in the outline alphabetically, by enabling the
sort button .
You can also filter all concurrent signal assignments from the outline
by enabling the Hide Signal Assignments button
.
Double-click in the Outline View to navigate to the corresponding
location in the editor.
If you enable the Link with Editor icon
and you click an
element in the Outline View, the corresponding code will be selected in
the editor.
Quick Outline View
You can also press Ctrl+O to open the quick outline.
This is just the outline view in a popup, but it also allows you to filter the shown elements.
This way, the quick outline can be used as a semanticCtrl+F, making it very easy to find a declaration in your open editor.
Pressing Ctrl+O again, when the quick outline is open, will also show the inherited members between the members of the current file.
Hierarchy View
The Hierarchy View shows the design hierarchy starting at a selected top level object. To choose a top level, open a file and right-click on an architecture (or entity or configuration or module). Then click Set as Top Level. Alternatively, you can click the Set Top button in the Hierarchy View to open a hierarchy top level selection dialog. You can use the filter field to quickly search for a certain top level.
The Hierarchy View automatically refreshes itself when you save your design files. If you have a really large design this could slow you down. You can turn the automatic refresh on and off by toggling the refresh button .
To highlight the current selection of the HDL editor in the Hierarchy View, enable the Link with Editor button . If the editor selection is part of the evaluated hierarchy tree, the corresponding hierarchy tree node will be selected.
The Hierarchy View also shows the generic and constants values of VHDL components in the hierarchy.
The internal compiler computes the generics and constants, even if they are passed down through the hierarchy, and even if arithmetic operations are used to define new values. If the value cannot be computed for some reason, the
Hierarchy View will report the value to be unknown.
When you double-click an object in the hierarchy, the Editor view is updated accordingly, possibly by displaying the contents of a different file.
Use the instantiations filter to hide everything except instantiations and structural statements.
You can launch a simulation with the button if you first set up a Launch simulator.
The Hierarchy View also offers an action Select required files, which selects all design files that are part of the current hierarchy, in the project explorer. This allows you to easily perform the same action on all files in the hierarchy. E.g. team commands, …
You can also export a CSV file with all dependencies of the selected element via the context menu: right-click and select Export Dependencies to CSV file.
Problems View
The Problems View shows problems (errors and warnings) related to your
code. These problems were reported either by the internal compiler or by
an external compiler tool.
You can navigate to the source of the problem by double-clicking on a
given problem. Problems can be sorted by clicking the column headers.
The content of this view can be customized via the View Menu . Possible customizations are
scope (workspace, project, selection), type, maximum number of
problems, …
Libraries View
The Libraries View shows the library mapping as well as the description style of the design units in all
projects. You can use it to navigate to a particular design unit in your
project. When you double-click on a file, the file opens in the Editor
view. If you right-click a file, you see the context menu which offers
extra commands for setting libraries and for setting the top level.
If you enable the Link with Editor button
, the Library View will
be linked to the Editor View. Now, the active file in the Editor View will
always be selected in the Library View.
Tasks View
It is common practice to add TODO and FIXME comments in your
code. Sigasi Studio automatically scans your comments for TODO and FIXME tags
and clearly highlights these comments with Task Tags. You can get a
nice overview of all task markers in your workspace in the Task View
(Window > Show View > Tasks).
You can configure extra tags in the Task Tag preference page:
Preferences > Sigasi > [Verilog/SystemVerilog | VHDL] > Task Tags
Bookmarks View
You can easily add bookmarks by right-clicking the line number where you want to add a bookmark.
You can get an overview of all bookmarks in the Bookmarks View
(Window > Show View > Others…).
The Bookmarks View can be used to delete bookmarks or navigate to the editor and other views.
The Block Diagram View displays a graphical (block diagram) view
of all architectures, modules, and their instantiations in your current VHDL or SystemVerilog editor.
VHDL processes are also shown in the block diagram.
This viewer automatically updates while you are editing your code and
gives a convenient way to visually inspect and navigate your code, even
when your code is still unfinished or broken.
You can open the Block Diagram View by right-clicking in the editor and
selecting Show In > Block Diagram. Alternatively, you can open the
view via Window > Show View > Other… > Sigasi > Block Diagram.
You can also double-click blocks, ports, or wires to navigate
to the corresponding HDL code. If you want to go into a block, you
have to select it, right-click and click Open Entity Declaration, Open Architecture, or Open Module.
To find an object in the Block Diagram, you can navigate from your code to the Block Diagram.
In your code, right-click a signal, port, process, or instantiation and select Show In > Block Diagram - just like when opening the Block Diagram View the first time.
If the Block Diagram already is open, the corresponding element is highlighted and the Block Diagram View is centered on it.
You can export the Block Diagram View to an image with the save
button. Both SVG and PNG are supported. Choose a *.svg filename for SVG export or a *.png filename for PNG export.
You can also export allblock diagrams of an entire project at once: Click Project > Export… > Sigasi > Block Diagrams export and select your project. All SVGs will be created in diagrams/blockdiagrams/ in your project.
The State Machine View displays a graphical (bubble diagram) view of all state machines in your current VHDL or SystemVerilog editor. This viewer automatically updates while you are editing your code and gives a convenient way to visually inspect and navigate your code, even when your code is still unfinished or broken.
You can open the State Machine View by right-clicking in the editor and selecting Show In > State Machines. Alternatively, you can open the view via Window > Show View > Other… > Sigasi > State Machines.
If you have documented your state transitions (i.e. the assignments), the comments will be added as text to the transitions in the view.
You can also double-click nodes or transitions to navigate to the corresponding HDL code.
With the button, you can toggle the display of comments on edge labels.
With the button, you can toggle the display of comments on edge labels. These labels show the code comments of the transition statements.
You also have to option to Zoom In, Zoom Out, or Zoom to Fit.
You can export state machines to an image with the save button. Both SVG and PNG are supported. Choose a *.svg filename for SVG export or a *.png filename for PNG export.
You can also export allstate machines of an entire project at once: Click Project > Export… > Sigasi > State Machine Diagrams export and select your project. All SVGs will be created in diagrams/statemachines/ in your project.
The Dependencies View visualizes the dependencies of your VHDL, SystemVerilog, or mixed language projects.
This view shows the relationships between your source files and makes it easy to see top levels and important packages.
The Dependencies View also makes it easy to detect orphaned files.
The view is automatically updated each time you save your files.
The Dependencies View has the following options:
show dependencies of the entire project. Uncheck to focus on the dependencies of the active editor only.
Group design files per library
Show design units inside design files. The design units are prefixed with an abbreviation of their kind (architecture, module, package, …" >}}
The Dependencies View can help you navigate too. Double-click a file name in the diagram to open the corresponding editor.
The Dependencies View can also be pinned. This prevents the diagram from changing when you switch editors.
You can export this diagram for documentation by clicking the save icon.
Documentation View
The Documentation View gives you a live preview of the automatic documentation Sigasi Studio can generate for your project.
With Net Search, you can find loads and drivers of a net.
A net is defined as a signal or port and all other signals and ports
that are directly connected to it. The loads are where you read the
value of the net and the drivers are where you write to this net.
To find the entire net of a signal or port, place your cursor on the
identifier and right-click. Now select Find Net. Alternatively, you
can press CTRL+SHIFT+H.
The Net Search View will appear. For big designs, it might take a
while before the results appear.
From the Net Search View, you can navigate to the VHDL code by
double-clicking the search results.
In the Preprocessor View, you can preview the expanded text of Verilog macros. This view automatically synchronizes with the active editor.
When you select text in the (System)Verilog editor, the expanded text will be highlighted in the Preprocessor View. This also works the other way: when you select text in the Preprocessor View, the corresponding, original source will be selected in the editor.
The Class Hierarchy View displays more information about the hierarchy of a class. It consists of a hierarchy tree
and a list of the class members. To open the Class Hierarchy of a class, click the class name, right-click and select Open Class in Hierarchy (or press F4).
Class Hierarchy Tree
The class hierarchy tree displays either the superclasses, subclasses, or both.
Command
Description
Class Hierarchy
Displays all superclasses and subclasses.
Superclass Hierarchy
Displays all superclasses and implemented interface classes.
Subclass Hierarchy
Displays all subclasses that extend or implement the selected (interface) class.
Show Qualified Class Names
Shows the qualified name next to each class.
Member List
The member list shows all members of the class that is currently selected in the class hierarchy tree.
Command
Description
Show Inherited Members
Shows or hides all members inherited from superclasses.
Sort By Defining Class
Sorts members by the class in which they are defined.
Hide Fields
Hides all fields in the members list.
Console View
When Sigasi Studio launches external tools (e.g. external compiler, documentation generation,…) the output is logged to the Console View.
This is a generic Eclipse view.
Different tools can open different consoles. You can switch between different consoles by clicking the -icon.
Minimap View
The Minimap View can be opened via Window > Show View > Other… and selecting General > Minimap.
This is a generic Eclipse view.
This view is another way to help navigation through large files.
It shows an overview of the entire active editor in a dedicated pane.
The part that is visible in the editor is highlighted.
The highlighted part of the Minimap View can be clicked and dragged to scroll through the Editor View.
The Editor shows the content of files and allows you to edit
files. It is a tabbed view such that multiple files can be opened simultaneously.
The currently selected file is the active file.
VHDL and SystemVerilog Editor
The VHDL and SystemVerilog (or Verilog) editors are optimized to help
you browse and edit VHDL and SystemVerilog code.
Most browsing and editing features are similar for both languages.
Sigasi Studio colors your code to make the structure more
clear. Unlike other tools, Sigasi Studio offers coloring based on the
meaning of a word, rather than just the syntax.
Sigasi Studio supports both syntax highlighting and semantic
highlighting. Syntax highlighting colors pieces of code according to
the lexical class the code belongs to, such as a keyword or string.
Semantic highlighting colors code according to its meaning.
For example, a constant is shown in another color than a signal.
Code highlighting is fully configurable for a number of
VHDL and Verilog and
SystemVerilog syntax and semantic elements.
Also, Color, background, style, and font can be
customized. Learn more about configuring
colors.
Rather than configuring every color yourself, you might want to have a
look at the supported Light and Dark themes. To switch between
themes, go to Window > Preferences > General > Appearance where
you can choose a theme. While it is possible to install additional
themes, only the Light and Dark themes are supported by Sigasi.
Type-time Syntax Error Reporting
Sigasi Studio marks VHDL and SystemVerilog syntax errors while you type. It will also report broken SystemVerilog preprocessor code.
Project Exploration and Navigation
Sigasi Studio offers powerful techniques to explore a file or project and navigate through it. This section covers: hovering, Occurrence Highlighting, Open Declaration, and Find References.
Occurrence Highlighting
If you click on an identifier, it is highlighted. In addition, all other occurrences of the identifier that refer to the same object are highlighted. Note that this occurrence highlighting is intelligent: it is not based on the identifier’s string value, but on the object that the identifier refers to.
You can turn occurrence highlighting on or off. Click the “Toggle Mark Occurrences” icon in the toolbar.
Find References
To look for occurrences of a given identifier in different files, place your cursor on the identifier and right-click. Now select Search References.
A search window will appear on the bottom of your workbench, displaying all occurrences of the selected identifier. You can easily navigate through all occurrences by clicking the Show Next Match arrow
and the Show Previous Match arrow in the search result view. Note that all occurrences are highlighted and marked with a small arrow at the left border of the editor for easy recognition.
Open Declaration and Hyperlinks
Open Declaration You can easily navigate to the declaration of any
port, signal, entity, etc. Place the cursor on the identifier,
right-click, and select Open Declaration. The editor immediately
switches to the line that declares the object. Since this operation is
so commonly used, it is assigned to the shortcut key F3.
Hyperlinks You can also navigate your code like a web browser by
clicking hyperlinks. If you press and hold the Ctrl key, hyperlinks will appear in your editor. If you click the link (while holding the Ctrl key), you will navigate to the target of the link.
Sigasi Studio offers the following links:
Link to Declaration: this has the same behavior as Open Declaration (F3)
Link to Matching Entity [VHDL]: this links a component declaration of an instantiation to the matching entity declaration. This also works for component generics and ports (Shift+F3)
Link to Matching Module [MIXED]: this links a component declaration of an instantiation to the matching Verilog module declaration. This also works for component generics and ports (Shift+F3). Modules that are instantiated as entity instantiations are also supported (label : entity work.verilogmodule port map (...);)
Link to Matching Architecture for entity declarations [VHDL]
Link to Matching When Clause [VHDL]: in finite state machines (FSMs) you can jump directly to the matching when part of your case statement from state transitions (Shift+F3)
Link to Open Declaration in Package Body [VHDL]: in packages you can jump directly to the matching declaration in the package body (Shift+F3). This also works in the opposite direction, Open Declaration in Package Body
Link to Open Declaration in Protected Type Body [VHDL]: in protected types you can jump directly to the matching declaration in the protected type body. This also works in the opposite direction, Open Declaration in Protected Type
Link to Include files in SystemVerilog sources (F3)
Link to Macro definition in SystemVerilog sources
URLs in comments
Hover
To learn more about the declaration of a given identifier, hold your mouse pointer over it.
After a short time, a popup shows you the name and datatype of the signal. This technique is called hovering.
The hover pop-up can show different kinds of information:
datatype
comments: inline documentation written at the declaration (association rules)
value: the value of constants
errors or warnings: a message, if the given identifier has an error or warning associated with it
binary/decimal conversion: for hexadecimal, octal, or binary values, the decimal equivalent
Since Sigasi Studio 4.1 the hovers also offer extra links that make it easy to navigate to the declaration, find references …
Autocomplete and Content Assist
Sigasi Studio provides powerful autocompletion capabilities. This means
that the tool can help you to complete identifiers and constructs as you are working on the code. Like other tools, the tool provides
autocompletion based on the HDL language. However, it goes much
further. It also provides autocompletion based on the design context. It can provide this additional level of intelligence as it knows all
objects that have been declared in the design.
Autocompletion Interface
Autocompletion may come from different sources, as will be discussed in the following sections. However, the user interface to initiate them is always the same. At any point, as you are entering code, you can press Ctrl+Space and the tool will suggest appropriate autocompletion.
Based on the Design Context
Sigasi Studio uses its knowledge of the design to provide intelligent
autocompletion that boosts your productivity tremendously.
The tool knows which objects are appropriate and which identifiers are
visible at any given point in the code. As you start typing and ask for
autocompletion, it will suggest the appropriate identifiers as
autocompletion candidates.
Sigasi Studio provides help to autocomplete:
component declarations
component instantiations
entity instantiations
module instantiations
case statements (based on variables/signals with an enumeration type)
SystemVerilog include paths ( `include "): triggering autocomplete between the double quotes will present a list of files and folders. If you select a folder, trigger autocomplete again to get completions in this folder.
Based on Templates
Sigasi Studio can help you to declare VHDL and SystemVerilog objects, using autocompletion based on templates.
Sigasi Studio comes preconfigured with templates for all common declarations and statements, including (for VHDL):
function, procedure
process
type: enum, file, range, array, record
signal, constant, variable
component
entity
architecture
entity/architecture pair
package/package body pair
and much more
Some autocompletions are templates that require further user input.
In such a case, the editor goes into a special template editing mode after the autocompletion has been performed.
You can use TAB to cycle through the items that have to be modified or completed.
When done, you can press ENTER to return to the normal editing mode.
The cursor will be placed at an appropriate position to continue working.
You can also configure your own templates.
To edit or create templates, go to Window > Preferences > Sigasi > VHDL or Verilog/SystemVerilog > Templates.
Here you get an overview of existing templates.
You can create New… templates, Edit… existing templates, or remove templates.
In the template editor, you can type ${ and press Ctrl+Space to see a list of the available variables.
Templates can be exported and imported. This is useful for sharing templates with colleagues.
Instantiating a Design Unit
Note: In other tools, this feature may be known as paste as instantiation or port translation.
Sigasi Studio knows all design units (entities, components, and modules) in the design and their port and parameter or generic interface, and can therefore automate much of the instantiation process. At the point in the code where you normally enter the design unit’s name, you can use autocompletion instead to suggest a list of possible design units. Upon selection, the tool will complete the instantiation with a generic or parameter list, and a port list with named associations. As an initial suggestion, each actual parameter will have the same name as its formal parameter. Of course, the actual parameter names need to be reviewed and edited by the user. Therefore, the editor will go into template editing mode after the autocompletion.
Note that design units will only be shown if they are visible in the current scope.
Automated consistent code formatting makes code more readable and helps developers understand code, whether working on their own code or when cooperating with colleagues.
You can set preferences for tabs or spaces under Window > Preferences > General > Editors > Text Editors.
Here you can set the tab width in spaces and configure to Insert Spaces for Tabs.
Whenever a tab is pressed, the corresponding number of spaces will be inserted instead.
You can also opt to Remove multiple spaces on backspace/delete so that removing leading spaces follows the indentation levels.
Format Code on Save
You can configure Sigasi Studio to automatically format your (System)Verilog and VHDL files when you save your source files via Window > Preferences > Sigasi > [VHDL | Verilog/SystemVerilog], next check Enable code format on save.
You can format (System)Verilog and VHDL files without opening them in the editor.
You can format an entire project. Right-click the project in the Project Explorer and select Source > Format.
Note that only files that are part of the build will be formatted.
You can format a selection of files. Select multiple files and/or folders in the Project Explorer and select Source > Format.
Any selected file, part of the build or not, will be formatted.
Any combination of resources can be formatted this way: multiple projects at a time, a project and a folder …
Other Editor Features
Code Folding
If you work with large files, you might want to hide certain pieces of your code. This can be done with code folding. Certain constructs, such as if-statements or process-statements can be folded so that they use a single line in the editor view. You can do this by clicking the little "-" symbol next to the statement.
You can also enable/disable code folding and perform other actions by right-clicking in the gutter (the small column to the left of your code) and selecting Folding.
Smart Caret Positioning
Smart caret positioning allows you to easily jump between words within identifiers, no matter whether you use camelCase or snake_case, by using Ctrl+Left arrow and Ctrl+Right arrow.
Sigasi Studio 4.15 added the option to disable smart caret positioning in identifiers, both in VHDL and (System)Verilog.
To change the setting, go to Window > Preferences > Verilog/SystemVerilog or Window > Preferences > VHDL where you can alter the selection of Smart caret positioning in identifiers.
Rename Refactoring
Right-click on any identifier (VHDL or SystemVerilog) and select Refactor > Rename element (Alt+Shift+R) to change the name of the declaration and all its references.
If you press Alt+Shift+R twice, you can preview the rename before applying it.
Full-screen View
Double-click on the editor tab to make it full-screen. You can also use Ctrl+M to achieve the same.
Block Selection
Note: In other tools, this feature may be known as column editing
or column select.
Block selection is an alternative to standard (paragraph) selection.
Block selection mode differs from standard selection mode in that it
allows to select rectangular regions, or to set the cursor over multiple
lines. Block selection is ideal for selecting vertical regions, for
example, a column of a table or all port names in a port map.
To toggle between normal and block selection modes use Alt+Shift+A
or press the Toggle Block Selection icon in the toolbar.
Structured Selection
Structured Select enables you to select VHDL or SystemVerilog code, based on its syntactic structure.
Shift+Alt+Up, expands the selection to the smallest syntax element that contains the current selection. You can then further expand the selection by invoking the action again.
Shift+Alt+Down, contracts the current selection to the nested syntax expression that still contains the current cursor position. You can then further contract the selection by invoking the action again.
Shift+Alt+Left, adds the syntax element left of the current selection to the selection. You can then further expand the selection by invoking the action again. You can also expand the selection in the other direction with Shift+Alt+Right
Add Parentheses or Create a String
When you select a region and press ( or [, the selected region is enclosed with the matching closing parentheses, ) or ].
When you select some text and press ", the selected text will be transformed into a string.
This works for both regular and multi-line strings.
This behavior can be disabled by unchecking Enclose selected region when typing parentheses or quotes in Window > Preferences > Sigasi > VHDL.
Show Whitespace
You can turn show or hide whitespace markers by clicking the Show Whitespace Characters icon in the toolbar.
Move and Duplicate Lines
You can easily move lines up and down by pressing: Alt+Up and
Alt+Down.
You can duplicate your current line, or the lines of the current
selection by pressing: Ctrl+Alt+Down.
The action to remove trailing whitespace is hidden by default. You can access it by pressing Ctrl+3, typing RTW, and then selecting the correct action. Alternatively, you can bind this action to Keyboard Shortcuts of your preference.
This action is being executed on the saved file, not in the editor. So before using this action, you have to make sure your file is saved.
Customize Color Preferences
There are several ways to customize color preferences in Sigasi Studio.
Choose the Eclipse Theme in the Window > Preferences > General > Appearance preferences menu.
Edit Eclipse Colors and Fonts setting in the Colors and Fonts sub-menu.
Change color setting for different text editor features in Window > Preferences > General > Editors > Text Editors
Annotation colors can be configured in the Annotations sub-menu.
Highlighting colors for differences can be configured in the Quick Diff sub-menu.
Syntax coloring for Verilog/SystemVerilog can be changed in the Window > Preferences > Sigasi > Verilog/SystemVerilog > Syntax Coloring preferences menu.
Syntax coloring for VHDL can be changed in the Window > Preferences > Sigasi > VHDL > Syntax Coloring preferences menu.
Multiple Screen Support
You can right-click the title tab of any view and select Detach to move the view into a separate window that can be dragged to another screen.
Alternatively, you can drag a view out of the current window to create a new window from it.
Once multiple windows are available, views can be dragged between screens.
The Editor View can be split or duplicated in
independent viewports that access the same file buffer.
There are 3 ways to split the Editor View.
Horizontal Split shows 2 viewports on top of each other.
Vertical Split shows 2 viewports next to each other.
Clone to a new Editor View.
This new Editor View can be detached so that
the same file buffer can be viewed on multiple displays.
To split the editor view, go to Window > Editor and select the desired action.
There are Keyboard Shortcuts
to toggle the Horizontal Split (Ctrl+_) and the Vertical Split (Ctrl+{).
There can only be a single horizontal or vertical split within an Editor View.
Multiple Editor Views can be cloned and re-arranged to obtain a custom layout with many views on the same file buffer.
Side-by-side Diff
Previous versions (local history or version control)
Comparing two files
Opening Project Files
The default way to open files in the VHDL and SystemVerilog editor is to double-click the files in the Project Explorer. But there are more methods to open files in your projects.
Open Resource
When you press Ctrl+Shift+R the Open Resource dialog opens. In this dialog, you can type a name or pattern to open a specific file name.
Open Design Unit
When you press Ctrl+Shift+D the Open Design Unit dialog
opens. In this dialog, you can search in the list of VHDL, Verilog,
or SystemVerilog design units and rapidly open the design unit you’re
looking for.
While typing, the corresponding matching characters in the design unit
descriptions are highlighted. You might notice how the design units are
not ordered alphabetically, but instead by best match.
Hint: there’s no need to bother writing special characters and upper
case letters in the search field. Our search filter will find your
design unit without them. It looks for consecutive matches in the design
unit descriptions, prioritizing those with longer and earlier matches.
Moreover, it offers smart case search: lower case letters match both
lower case and upper case letters, but you can narrow down the search by
using upper case letters, those only match themselves.
In addition to the powerful features of an Eclipse editor, the VHDL
editor that comes with Sigasi Studio supports a number of advanced editing
features that are specifically useful for VHDL editing. These are
described in this chapter.
Code Highlighting
Highlighting Classes for VHDL:
Syntax : Comment, Keyword, Number, String, Task tag
Note: In other tools, this feature may be known as paste as
component or port translation.
If you want to use instantiation based on a component (as opposed to
direct instantiation) you need to associate an entity with a component.
Sigasi Studio can automatically declare a component for an existing entity. At
the point where you normally enter the component name, you can use
autocompletion instead to show the list of available entities. Upon
selection, the tool will automatically complete the component
declaration.
Type Conversion
In VHDL design you need to do a lot of type conversions. Sigasi Studio’s
autocomplete functionality can help you with those. Put a dot (.)
after the element you want to convert, and the autocomplete suggestions
will appear. The conversion functions have descriptions like convert type and convert to ...
Smart Indentation
When you press enter, Sigasi Studio automatically adjusts the indentation of
the current and the new line. Depending on the content of the preceding
line, Sigasi Studio will automatically increase or decrease the indentation
level. E.g. an extra indent after an if-statement and removal of an
indent for the matching else-clause.
You can enable/disable this feature via Window > Preferences >
Sigasi > VHDL by toggling the Enter adjusts indentation on current
and next line setting.
Tabs vs. spaces: This feature inserts tabs characters or spaces,
according to your preferences.
Press Ctrl+Shift+F to format your current VHDL file.
This includes:
indentation
spacing between keywords and references
vertical alignment of certain symbols like `<=``
Context-based
Sigasi Studio’s formatter is context-based and tries to respect the author’s style. So depending on your source style, the formatter might make different choices.
One example is the decision to format a conditional signal assignment on one, or multiple lines. Sigasi Studio makes this decision based on the position of the first else keyword. If you put the else keyword on the first line, the formatter will put everything on one line. If you put the else keyword on a new line, the formatter will use multiple lines for the assignment.
demo<=(others=>'0')whenenable='1'else(others=>'1')wheninput='1'-- else on new lineelse(others=>'X');
Note about broken code: If your VHDL source file contains syntactical errors, the formatter cannot always figure out appropriate formatting. For this reason, the formatter is programmed to stop applying (whitespace) changes beyond unsupported syntax errors.
Configuration
You can set your preferences for tabs or spaces under
Window > Preferences > General > Editors > Text Editors.
VHDL-specific code formatting can be configured at Window > Preferences > Sigasi > VHDL > Formatting:
Preserve newlines: this option configures the formatter to not add or remove any newlines in your code.
Vertical alignment: this option configures the formatter to vertically align consecutive declarations and statements for example on <= or :.
Lowercase/Uppercase keywords: when this option is set to UPPERCASE the formatter will convert all VHDL keywords to uppercase.
When this option is set to lowercase, the keywords will be converted to lowercase.
When this option is set to ignore, the case of keywords won’t be changed by the formatter. Note: A Sigasi Studio XL
license is required for this option.
Alignment column for trailing comments: this setting configures what column Sigasi Studio aligns trailing comments to. The default is 40, you can choose -1 to not align trailing comments.
Correct Indentation Only
Sigasi Studio can also correct the indentation of your code without making any other changes. Inside a VHDL editor, open the context menu and click Source > Correct Indentation, or hit Ctrl+I. This only changes whitespace at the start of your lines.
If you select code first, only the code in the selection will be indented.
Disable Formatting in Defined Regions
You can disable the formatter for defined regions in your VHDL source files by add off and on tags:
off tag: -- @formatter:off
Turns of the formatter until an on tag is encountered
on tag: -- @formatter:on
Reenables the formatter following an off tag
VHDL 2019 Tool Directives
Sigasi Studio 4.16 introduced VHDL 2019 tool
directives, which are a simplified version of the preprocessor found in
SystemVerilog or the C family of languages.
Tool directives allow to conditionally enable code based on tool type,
debug mode, or really any other custom variable.
You can edit the defined tool directives by right-clicking your project and then going to Properties > VHDL Conditional Variables.
Stuttering is an editing technique popularized by Emacs, that lets you
type certain things really fast. Stuttering means that you tap a certain
key twice and it expands to something more complex. For example, press
the period key . twice, and the editor will expand it to a right
arrow =>. Stuttering works like double-clicking: if you type keys
slowly, the stuttering mechanism will not be triggered.
The following stuttering keys are available:
Keys
Effect
,,
<=
..
=>
;;
:=
Stuttering can be disabled or enabled through the Enable stuttering option in the Window > Preferences > Sigasi > VHDL menu.
Verilog and SystemVerilog Specific
In addition to the powerful features of an Eclipse editor, the Verilog and SystemVerilog
editor that comes with Sigasi Studio supports a number of advanced editing
features that are specifically useful for SystemVerilog editing. These are
described in this chapter. Currently, Verilog 2005 (IEEE 1364-2005) and SystemVerilog 2017 (IEEE 1800-2017) are supported.
Code Highlighting
Highlighting Classes for Verilog and SystemVerilog:
Making a typo in the file name of an `include causes swarms of errors. To prevent this, you can just press Ctrl+Space
between the double quotes of the include directive. You’ll be presented with all the files visible from
your current include path.
Smart Indentation
When you press enter, Sigasi Studio automatically adjusts the indentation of
the current and the new line. Depending on the content of the preceding
line, Sigasi Studio will automatically increase or decrease the indentation
level. E.g. an extra indent after a module and the removal of an indent for
the matching endmodule.
You can enable/disable this feature via Window > Preferences >
Sigasi > Verilog/SystemVerilog by toggling the Enter adjusts indentation on
current and next line setting.
Tabs vs. spaces: This feature inserts tabs characters or spaces,
according to your preferences.
Press Ctrl+Shift+F to format your current Verilog or SystemVerilog file.
The default formatter implementation corrects indentation only.
Since Sigasi Studio 4.15, Sigasi ships with Verible built-in. Verible is an ambitious SystemVerilog formatter that is agnostic to macro invocations and includes and therefore produces a consistent formatting result even in heavily preprocessed code.
You can enable the Verible formatter for your installation by going to Window > Preferences > Sigasi > Verilog/SystemVerilog > Formatting.
Under Select formatter, you can choose between the default Sigasi formatter which corrects indentation, and using the Verible formatter.
Sigasi ships with a recent Verible version by default.
If you’d rather run your own Verible installation, this can be achieved in Window > Preferences > Sigasi > Verilog/SystemVerilog > Formatting > Verible.
To select your own Verible binary instead of the one that comes with Sigasi, select the Use external Verible formatter instead of bundled one: option and configure the Verible installation path: option.
This page also allows you to customize the Verible formatting rules, both for the built-in and the external Verible binaries, by pressing the Edit… button.
For maximal compatibility, you need to make sure the Eclipse setting to Insert spaces for tabs is enabled and that the Displayed tab width is matching the Verible configuration.
In the Verible configuration page, configurations are grouped in the following tabs.
Indents and Wrapping
Ports and Parameters
Types
Statements and Expressions
If you want to undo your changes, you can use the Restore Defaults button, either per tab or for the entire dialog.
After applying your configuration changes, press the OK button.
To see this in action, you can have a look at our screencast.
The Verible website and README contain more information.
Verilog Version
You can configure the Verilog version via Window > Preferences > Sigasi > Verilog/SystemVerilog
and select whether *.v files are treated as Verilog (IEEE 1364-2005) or SystemVerilog (IEEE 1800-2017). *.sv files are always treated as SystemVerilog.
Include Paths and Initial Preprocessor Definitions
The fastest way to add an include path is to run the Quick Fix on `include errors in the editor.
You can configure the include paths of your SystemVerilog projects in the Verilog Preprocessor property page.
Right-click your project and select Properties > Verilog Preprocessor.
Here you can Add and Remove include paths using the buttons on the right.
You can also move the order of the include paths using the Up and Down buttons.
The Import... and Export... buttons can be used to transfer a semicolon-separated (;) list of include paths from and to the clipboard.
In the Initial preprocessor definitions field, you can configure definitions that are set before other files in the project are processed.
This allows you to, for example, set global defines without an explicit include statement.
When you hover over a SystemVerilog preprocessor directive (e.g. include ...), Sigasi Studio shows the preprocessed text.
You can find a convenient link to open the Preprocessor View at the bottom of this hover.
Ctrl+Click on `defines (or F3) will lead you to the corresponding declaration.
Autocomplete will also offer you a list of all visible `defines.
In the Preprocessor View, you can preview the expanded version of your preprocessed SystemVerilog source files.
You can call Sigasi Studio from the command line to open files. Just run
sigasi yourFile.vhd. You can also drag and drop files on the Sigasi Studio
icon to open them.
You can specify a linenumber by appending +yourLineNumber to the
command line. For example: sigasi test.vhd +10 will open test.vhd at
line 10.
You can also specify the project location with the -p <project path> parameter.
If the specified project was not open in the workspace yet, this will import
and open the project in the workspace.
Note that the VHDL file you specify on the command line has to be in an
open Sigasi project to enjoy all of Sigasi Studio’s powerful editing and
navigation features. If the file you open from the command line is not
in a Sigasi Studio project, Sigasi Studio opens the file as an external
file. This is nevertheless really handy for quick
edits.
This feature enables you to configure Sigasi Studio as default editor for other
EDA tools.
Note You could get a firewall warning when you start Sigasi Studio because
Sigasi Studio opens and listens to a port (4444 by default). This is necessary
for the communication between the running Sigasi Studio instance and the
command line executable. Configure your firewall to allow Sigasi Studio access
for opening this port. Update Since Sigasi Studio 4.17.2, the listener no longer listens to port 4444.
A random free port will be used, one per user on multi-user systems.
Eclipse Plugin
Eclipse plugin users can also use this feature but need to specify a few
more command line options. You have to type
eclipse -application com.sigasi.runner.open instead of sigasi. For
example: eclipse -application com.sigasi.runner.open test.vhd +10 will
open test.vhd at line 10.
Other command line options
You can add some extra parameters to Sigasi Studio to modify the behavior.
-help : show simple command line usage information
-data <location> : specifies the workspace location
-noSplash : do not show the splash screen at startup
-consoleLog : log all debug information in the console (in addition to the regular log file)
-refresh : force refresh of workspace
-showLocation : show workspace location in title bar
-application org.eclipse.ui.ide.workbench : use the default Eclipse workbench launcher instead of the Sigasi Studio workbench launcher.
This avoids conflicts on port 4444 when running Sigasi Studio with multiple users on the same server.
Refer to the setup page for more information.
--launcher.openFile <somepath> : open the Import Projects dialog to import a new or existing project into the workspace
-Dcom.sigasi.hdt.disableAutomaticTutorial : suppress the creation of the tutorial projects in empty workspaces.
-Dswt.chromium.path=/home/user/blub : extract the Chromium binaries in blub
External Files
You can edit VHDL files without setting up a project.
When a file that doesn’t belong to a project is opened in Sigasi Studio, this
file is called an external file and it will be opened in single file mode.
Single file mode is a limited environment in which not all Sigasi Studio
features are available. Navigation only works within a file. For that reason
missing declaration are not flagged as errors.
When I double-click a VHDL file, I want it to open with my favorite VHDL editor. Sigasi Studio, obviously.
Here is how to set this up in MacOS:
Find a VHDL file in the Finder
Right-click and select Get Info
Select Open with > Other… and find your Sigasi Studio application
Click Change All… so that all other VHDL files will also get opened with Sigasi Studio.
Repeat this procedure for *.vhd files and for *.vhdl files.
Intel Quartus
In Intel Quartus, open the preferences page in Tools > Options >
General > Preferred Text Editor.
As command-line options, you should have %f +%l -p %p. Optionally you
could add -noSplash to skip the splash dialog.
AMD/Xilinx Vivado
You can configure Sigasi Studio to be the preferred editor for AMD/Xilinx Vivado.
In AMD/Xilinx Vivado, click Tools > Settings…
Open the Tool Settings > Text Editor tab
Locate the Current Editor drop down menu and instead of ‘Vivado Text Editor (default)’ select ‘Custom Editor…’
If needed click the … button and in the pop-up dialog enter:
<path to Sigasi Studio>/sigasi.exe [file name] +[line number]
Click OK to close the dialog and OK to close the Settings window.
Extra steps on Linux
If your log file contains warnings about LD_LIBRARY_PATH being set to an incompatible value or if you get an error telling the JVM terminated, you can correct this by making sure LD_LIBRARY_PATH and (optionally) LD_PRELOAD are empty when launching Sigasi Studio.
Do this by e.g. creating a script to launch Sigasi Studio and call that script from within the Vivado Text Editor settings.
Extra steps for the Sigasi Studio plugin on Windows
If you use the Sigasi Studio Eclipse plugin on Windows, you might need to take some extra steps
before you can open files from Vivado in Sigasi Studio.
Make sure to close Eclipse before making the changes below.
In your Eclipse installation
In eclipse.ini remove these 2 lines
--launcher.defaultAction
openFile
In configuration/config.ini
replace osgi.instance.area.default=... with osgi.instance.area=@nodefault - note the removal of the .default suffix
replace eclipse.application=.... with eclipse.application=com.sigasi.runner.open
In Vivado configure the custom editor with the following setting
C:\....\eclipse.exe [file name] +[line number]
The first time you might need to pick a workspace and enable the use this as default and do not ask again option.
AMD/Xilinx ISE
To configure Sigasi Studio as default VHDL editor in AMD/Xilinx ISE:
In AMD/Xilinx ISE, Click Edit > Preferences and ISE General > Editors
Select Custom instead of ISE Text Editor
If Sigasi Studio is on your path enter sigasi.exe $1 +$2 (Windows) or sigasi $1 +$2 (Linux).
If Sigasi Studio is not on your path, use the absolute path instead. If there are spaces in this
path, you need to enclose the path in curly braces . For example:c:\\My\ Applications\sigasi\sigasi.exe $1 +$2.
If you now open any VHDL file in AMD/Xilinx ISE, Sigasi Studio will automatically open the selected file.
You can find more info on configuring AMD/Xilinx ISE to work with external editors in the AMD/Xilinx documentation.
HDL Designer
To configure Sigasi Studio as external editor in HDL Designer:
In HDL Designer, click Options > Main
Click the Text tab
Press the Setup… button in the Editor section to open the Editor Command Setup dialog.
Fill the Name, Command and Arguments sections as shown.
Click the Add button to add Sigasi Studio to the list of available editors.
Press OK to close the dialog.
Press the Setup button in the HDL Viewer section and repeat this procedure from step 4.
You now can select the Sigasi entry in the list box for the Editor and HDL Viewer sections.
From now on you can double click on a file or a line in a file - for example by selecting an architecture or an entity - and Sigasi Studio will open the file at the correct location.
In addition to syntax validation, Sigasi also checks your code for
semantic problems (Linting, or Linter checks). Some of these
problems can be automatically resolved with Quick Fixes. Both syntax
checking and linting happen at type-time: new markers appear as you are
typing your code.
Linting
Code Lint is defined as code that is strictly correct according
to the language definition, but still suspicious or problematic.
Sigasi has a built-in linter, which provides info about code lint
in the design.
In addition to code linting, Sigasi can also check that file
headers and symbol names (entities, signals, variables…) follow
certain patterns. This is discussed under naming conventions.
Marker Icons
marks an info message that can be resolved automatically with a Quick Fix.
marks an info message.
marks a warning that can be resolved automatically with a Quick Fix.
marks a warning that cannot be resolved automatically.
marks an error that can be resolved automatically with a Quick Fix.
marks an error that cannot be resolved automatically.
Configuring the Linting Rules
The Sigasi linter has reasonable defaults for the configuration
of reported lint problems. However, the severity level of certain
classes of linting rules is configurable for additional flexibility.
Furthermore, some linting rules, such as the VHDL maximum line width
rule, can be tweaked
to your preference. The configuration interface to configure linting
rules for the entire workspace is available through:
For each linting rule, you can set the severity of non-conformities
in all code or in RTL-specific code. For some linting rules, more
configuration options will appear in the sidebar. Look into the
documentation of the specific rule
for more details on their effect.
Suppressing Warnings
Specific warnings can be suppressed in your code by adding a @suppress comment (-- @suppress for VHDL and // @suppress for SystemVerilog), on the same line as the warning.
You can limit the suppression to a specific warning by putting a prefix of the warning message between quotes after @suppress. Sigasi also recommends adding a reason why the warning was suppressed by adding an extra comment after @suppress:
<line with warning> // @suppress "Warning message prefix" Reason why warning is suppressed
Since Sigasi Studio 4.2 the @suppress comment also suppresses Errors.
Since Sigasi Studio 4.3 warnings have a quickfix to automatically add the @suppress comment with a matching warning message prefix.
Export Markers
You can export markers for the entire project via the Export… menu. This feature is quite useful, if you want to focus on the markers without generating documentation.
First you have to check the box that is located next to the name of your project. You can then select the format of the file (either HTML or CSV) to be generated.
Markers Report
In the report you can see all the markers in your project. The entries in the report are layed out in six columns:
Description: shows what the marker is about
Location: shows in which file the problem is marked
Line number: line number of the marker
Type of the marker
Severity: severity that is set in the linting preferences
Note that suppressed markers are also listed in the report (see the last line in the image below).
No Linting for Common Libraries
Common Libraries are considered to be production ready libraries.
Linting is skipped for all files in the Common Libraries folder.
Naming Conventions
Sigasi can check whether all sorts of names in the design -
entities, instances, modules, signals, variables… - follow
particular patterns. This may help designers to follow their
company’s or team’s coding rules. For example, coding rules may
prescribe that signal names must have a s_ prefix, that generics
names must be written in capitals, or that variable names must use
CamelCase. A naming convention rule is empty by default, which means
that the particular rule is not checked.
In addition, Sigasi can also check for header comments of files,
design units, subprograms, etc. This could for instance be used to
check whether a copyright notice or disclaimer has been included in
the file header comment.
Workspace wide naming conventions settings are accessed via
Window > Preferences > Sigasi > Verilog/SystemVerilog > Naming Conventions for Verilog and SystemVerilog, and
At the top, you can set the severity of naming convention non-conformities.
Below, you can enter the validation patterns.
Patterns use the RE2/J regular expressions syntax.
Note that names are not validated if the corresponding validation pattern is empty.
Note that you can add two patterns per name: a valid pattern which
the name must match (a marker will appear if it does not match) and an
invalid pattern which the name cannot match (a marker will appear if
it does). You can set either or both patterns per name.
You can also configure naming conventions per project, or even per
file or folder. Documentation on how to do that is
here.
Quick Fixes
Some of the VHDL lint problems can be automatically resolved with Quick Fixes.
These problems have markers annotated with a lightbulb icon (like ).
To trigger a Quick Fix, click the problem marker or press Ctrl+1 and select the Quick Fix.
Language-specific Linting Rules
The currently available linting rules are described in detail on the following pages.
Sigasi Studio offers 2 ways of configuring the severity of linting checks.
For the entire workspace, through the Window > Preferences dialog as described above.
You can override these setting by creating a settings file for your projects.
In each project, you can override the coding rules settings. You can override rules for the entire project, for folders in the project, or for individual files.
Errors/Warnings Property Page
To configure the severity level, right click the project (or file or folder) in the Project Explorer and select Properties > VHDL Errors/Warnings or Properties > SystemVerilog Errors/Warnings.
On the top of the dialog, select Enable project specific settings to activate the rule configuration on a project base.
Enabling this setting will override any settings specified at the workspace level.
For each of the available rules, you can choose from a drop-down list or you can set all severities at once by using Ctrl-A.
Note that choosing the default setting does not inherit from the workspace settings.
It will apply the Sigasi built-in default for a linting rule.
Project settings are stored in this settings file:
Where ${path} can be <project> (literally, with brackets!) to set the severity of the entire project,
/path/to/folder to set the severity of an entire folder,
or /path/to/file.vhd to set the severity of a specific file.
The valid values for the parameters are documented on the individual linting rule pages.
They are described according to these rules:
{value1|value2} means that either value1 or value2 must be used,
e.g. true for {true|false} or bit_vector for {enumeration|bit_vector|std_logic_vector}.
${integer} means the value must be an integral number, e.g. 5.
If the number must fall within a range, it is specified in a comment.
[keyword...] means the value is any number of keywords (or other strings) separated by tab characters,
e.g.
ENTITY PACKAGE
If any of the strings must contain a tab character or a single quote, escape it using a single quote.
For example, below is a list of 2 items, the first a<Tab>tab and the second a'quote.
a' tab a''quote
${regex} means the value must be an RE2/J regular expression, e.g. 0|1.
Whitespace in keys must be escaped with a back slash (\). You can add comments
with #.
The table below lists the Verilog and SystemVerilog linting rules that can be checked automatically by Sigasi.
The availability of linting rules depends on the license requirements.
The table below lists the VHDL linting rules that can be checked automatically by Sigasi.
The availability of linting rules depends on the license requirements.
Sigasi Studio supports a number of ways to work with external tools such as
simulators. Different techniques offer varying degrees of flexibility
and automation.
Most people will want to set up their external compilers
so that Sigasi Studio can use them to compile and start simulations.
Another way to compile your project is to export your project to a CSV (comma separated values) list
of all the files in your project, in the correct compilation order.
Learn more about how to export your project’s file list.
The third, and more advanced way of working with compilers or simulators
is to use the standard Eclipse mechanisms of builders and external
tools.
By creating a builder,
you can arrange for an external tool to be run automatically when a
Sigasi Studio project is rebuilt. By default, this happens each time you save a
file. External Tools Configuration
allow you to call any program or script from within the Sigasi Studio GUI. You
have to write and maintain the scripts yourself, but you have complete
flexibility as to what is in the scripts.
External Compilers
If you have a simulator or lint tool installed, you can use this for two
purposes:
Save-time Compilation: Compile and
check your files each time you save. Any errors or warnings will
show up in the file, on the line number of the problrem
Launch Simulator: Start the
simulator in its own window, ready to run a simulation.
If an external compiler is enabled, you can also start a simulation from
Sigasi Studio. You can start a simulation by first selecting your top level
in the Hierarchy View. Next click the
Simulate button in the hierarchy
view to launch the simulator gui with an elaborated design ready for
simulation. Sigasi Studio opens a new console for each simulation launch. You
can terminate a simulation by clicking the Stop icon
.
When you launch a simulation, Sigasi Studio opens a new console in the Console View
You can switch between different consoles by clicking the -icon.
Configure external compiler
You can configure the external compiler settings by clicking Window >
Preferences > Sigasi > Toolchains. There is a sub-page for each
supported toolchain. Before you can enable a toolchain on the main page,
you must specify its installation path. Clicking Restore Defaults on
a Toolchain page will automatically fill in the installation path if
your toolchain is installed on a default location. After you press
Apply, you can select your toolchain on the Sigasi > Toolchains
page.
For some toolchains you can specify extra command line arguments. Note
that these preference pages support Eclipse
Variables
which allow you to more easily share settings in a team.
Environment variables are supported too.
If you want to use the $HOME environment variable, you can call this variable by typing ${env_var:HOME}.
List of toolchains
By “toolchains”, we mean any tool or set of tools that processes VHDL or
Verilog code, and that is supported by Sigasi Studio. At this time, external
compiler include simulators and lint tools, but in the future it could
also include synthesis tools.
For each toolchain Sigasi Studio can support any combination of the following:
Sigasi Studio can use an external VHDL or Verilog compiler for additional code validation. At this time, Sigasi Studio supports:
vcom / vlog / vsim style compilers. These compilers include Aldec Riviera-PRO and from Mentor Graphics ModelSim and QuestaSim.
isim compiler from AMD/Xilinx.
ncsim compiler from Cadence Incisive.
Catching bugs earlier is cheaper than catching them late. Traditionally,
the first errors are found when the hardware designer decides to run a
simulation. At this time, the simulator’s compiler tool will detect
errors and fail. At Sigasi we think that this is too late. Problems
should be detected as soon as possible.
Sigasi Studio adds two extra layers of error detection to catch problems
earlier. First, there is the type-time error detector. As soon as
the designer writes an error, it is marked in the text much like a spell
checker in a word processor. Second, as soon as you save a file,
Sigasi Studio calls the external compiler for further analysis. All errors that
the external compiler finds are marked inside your file, so that you can
find and fix them easily. Sigasi Studio intelligently controls the external
compiler incrementally and only recompiles design files that need
recompilation.
All output from external compilers is logged in Sigasi Studio’s console view
for your convenience. Paths to your design files are automatically
converted to hyperlinks to ease naviation.
The table below lists some examples of VHDL errors that are detected in
Sigasi Studio at type time, at save time and with the external compiler
integration.
Check
Type time
Save time
Save time compile
Syntax errors
yes
yes
yes
Undeclared signals
yes
yes
yes
Multiple files
no
yes
yes
Data type mismatch
no
no
yes
Multiple drivers
no
no
yes
Libraries
Libraries are fully supported. But note that Sigasi Studio does not send Common
Libraries to the external compiler for compilation. These libraries are
expected to be pre-compiled. Contact support@sigasi.com if you want to
add more libraries to this list.
If your project root contains a modelsim.ini file, Sigasi Studio will add this
file to the vcom command with -modelsimini. This allows you to
configure custom settings for Mentor’s vcom.
External Tools Configuration
Select Run > External tools > External Tools Configurations to get
started, or use the icon.
To create a new configuration, first select
Program, then click
.
Enter all necessary information to start your external tool:
Name: The name for this configuration.
Location: The location of the executable. You can browse for programs and scripts in your workspace or programs on your file system.
Working Directory: The working directory for your program.
Arguments: The arguments, if any, to your program.
You can test your tool configuration with the Run button.
The following example screenshot shows how to set up configuration to
run a simulate.sh script from within Sigasi Studio.
The following example screenshot shows how to set up a configuration to
run make clean on a Linux machine.
To run the external tool just select the configuration from the dropdown
menu on the -icon. You can rerun the
last configuration by simply clicking
.
Variables in Arguments
In the arguments field you can use variables, which are automatically expanded when the external tool is run.
This allows you to do things like adding the currently selected file in the file explorer as an argument for an external tool configuration (${resource_path}).
Sigasi Studio adds following variables and parameters for VHDL and (System)Verilog projects:
Variable Name
Description
${library:<argument>}
Get the library name of <argument>. For example, to the get the library of the currently selected resource use ${library:${resource_path}}
${sigasi_toplevel}
Get the name of the current top level: library.name
${sigasi_toplevel:short}
Get the name of the current top level without library: name
${sigasi_toplevel:project_path}
Get the path of the current top level’s project root
Creating a Builder
An external tool configuration as described in the previous section
makes it easy to run an external tool, but you still have to do so
explicitly. For some programs, such as the make utility, it makes
sense instead to do this automatically upon a change in your project.
This functionality can be accomplished by a builder. We will show how to
create a builder for a Modelsim Makefile as an example.
To create a builder, right-click your project and select Properties >
Builders.
Click New… and the builder configuration window will pop up:
You will be asked to select a configuration type:
select Program.
Next, configure the builder in a configuration window pop up window:
Name: The name of your builder, e.g. ModelSim.
Location: The location of the program, e.g. /usr/bin/make.
Working Directory: The working directory for your program. For example, click Browse Workspace… and select the root folder of your project.
Arguments: The arguments to your program, e.g. --makefile=Makefile.vsim all.
With the default settings the ModelSim Makefile will only be run during
a manual build or after a “Clean”. To make sure Sigasi Studio runs make
every time you save a change to a file, click the Build Options tab
and check the During auto builds checkbox.
After configuration, the new builder will appear in the builder list.
When you close the builder configuration dialog windows, the new builder
will automatically be run. In our example of a Modelsim Makefile,
Modelsim’s messages will appear in the console view.
For the specific case of Modelsim, warnings and error messages in the
console are made clickable. When you click a message, the corresponding
location will automatically be opened in the Editor view.
You can add as many extra builders as you want. This can be useful for
additional linting tools or code generators.
Intel Quartus integration
If you are using Intel Quartus 12.1 or higher, you can use Sigasi Studio as
preferred HDL editor.
If you use the Sigasi Studio/ Intel Quartus integration, you can
easily open VHDL files by double clicking on them in Quartus. Sigasi
Studio will be aware of the entire Quartus project, so that you can
perform project-wide searches and navigation actions in Sigasi Studio.
Furthermore, if you add or remove files in the Quartus project, these
changes are automatically applied in Sigasi Studio.
Note: If you want to set up a project independent of Intel Quartus,
please read the documentation on setting up a project.
Setting the preferred editor
While importing a Quartus Project in Sigasi Studio, you have the
possibility to configure Sigasi Studio as preferred editor
in Intel Quartus.
This offers the ability to open files in Sigasi Studio from within Quartus.
Open a Quartus Project in Sigasi Studio
After you have configured Sigasi Studio to be the preferred editor in
Quartus, you can open files by double clicking on them in Quartus.
Sigasi Studio will import entire Quartus project and your file will open
in the Sigasi Studio editor view. If you make changes to your Quartus
project (like adding or removing files), these changes are reflected in
Sigasi Studio as well.
The first time you import your project, it may take a few minutes. After
that, you can leave Sigasi Studio open and double-click other files in
Quartus to open them in the Sigasi Studio editor view.
If your Quartus Project File (.QPF file) contains a reference to a
file that does not exist, Sigasi Studio will show an icon for that file with
the broken link icon .
Quartus Preferences
The first time you import a Quartus project, Sigasi Studio will ask for the
Quartus installation location. Sigasi Studio needs this path to find the
Quartus libraries. You can change the Quartus installation
location by selecting Window > Preferences > Sigasi > Toolchains.
Add files to your Quartus project in Sigasi Studio
To add a file to your Quartus project, you can use the default New
VHDL file wizard of Sigasi Studio (File > New > VHDL File).
Note that Quartus does not automatically update its UI after you add
files to your project. In order to update the files list, you should run
a work flow action in Quartus, like starting a compilation.
AMD/Xilinx integration
Setting the preferred editor
To open the Sigasi Studio editor from AMD/Xilinx, you first have to configure Sigasi Studio as preferred editor in Vivado or ISE.
You can change the AMD/Xilinx Vivado installation location by selecting Window > Preferences > Sigasi > Toolchains > Xilinx Vivado.
Sigasi Studio needs this path to find the AMD/Xilinx Vivado libraries.
ISE
You can change the AMD/Xilinx ISE installation location by selecting Window > Preferences > Sigasi > Toolchains > Xilinx ISE.
Sigasi Studio needs this path to find the AMD/Xilinx ISE libraries and to run the ISim compiler and simulator.
Export
You can export a list of all HDL files in your project, sorted in the correct compilation order.
You can use your own simple scripts to manipulate such list and run any EDA tool, including simulators, synthesis and linter tools.
To export a comma separated value (CSV) list of files in your project, right-click your project and select Export….
In the Sigasi category, select CSV File. Then select the project you want to export.
As a result, you get a file named compilation_order.csv, which lists the HDL files in your project in a valid compile order.
This file will use relative paths, except when the file is on a different drive (on Windows).
Auto-export
You can also configure Sigasi Studio to auto-export this CSV file, every time the dependencies change.
Right click on the project you want to auto-export in the Project Explorer, and select Properties and Sigasi Auto Export.
If you do not set a fixed top level name (i.e. empty top level name in the property page), Sigasi Studio will use the current top level in the Hierarchy View as input.
Note that this only works if the top level belongs to the selected project.
This information is stored in .settings/com.sigasi.hdt.shared.ui.prefs in your project.
VUnit is an open source unit testing framework for VHDL and SystemVerilog. VUnit helps you to write tests more easily and run them frequently.
Sigasi Studio can help you manage VUnit projects and enables you to run and inspect test results straight from the IDE.
When you import a VUnit project or add VUnit support to an existing project, Sigasi Studio runs VUnit in the background and automatically adds the correct libraries - as specified by the VUnit script - to your project. It also shows error markers in the VUnit script (run.py) if anything goes wrong.
Since Sigasi Studio 4.14, the library mapping of the project is automatically updated based on the contents of the VUnit run.py script.
VUnit project setup in Sigasi Studio
Prerequisites
VUnit version 4.5.0 or higher is required.
Sigasi Studio needs to know where VUnit is installed. If you installed VUnit using pip install vunit_hdl and Python is in your path, then Sigasi Studio should find your VUnit installation.
To verify whether Sigasi Studio can find your VUnit installation, go to Window > Preferences > Sigasi > Toolchains > VUnit and check the read-only VUnit installation path field.
If your Python installation is not in the path, you can configure it here in the Python executable location field.
If you have installed VUnit in a dedicated location, you should add the VUnit location to the $PYTHONPATH and make sure the $PYTHONPATH variable is visible to Sigasi Studio.
When you’re installing VUnit in a virtualenv, make sure to launch Sigasi Studio from within the terminal after activating the virtualenv.
If you installed VUnit from the Microsoft Store, you might get an error message when trying to select the Python executable.
To use Python outside of Windows Store apps, Python needs to be installed using an installer from https://www.python.org/downloads/windows/.
You should make sure that the python run.py --version command only returns the VUnit version number. Additional output will prevent Sigasi Studio to parse the VUnit version number correctly and will result in errors.
Import VUnit Project
To import an existing VUnit project, click File > Import… > Sigasi > Import a VUnit project. Next, select the VUnit script (run.py) and the location for the Sigasi Project.
The VUnit project repository comes with a number of example projects which can be imported this way. If you first specify the Python Script Location, the Project Location will be set automatically.
Add VUnit support to an existing Sigasi project
You can also add VUnit support to an existing project: Right-click your project and select Configure > Add VUnit support. Next, select an existing run.py script or let Sigasi create an example script.
VUnit project configuration and troubleshooting
The VUnit integration in Sigasi Studio gives useful feedback in the VUnit Console View.
To open this view, first open a console (Window > Show View > Other… > General > Console) and in the Console View toolbar click the triangle () next to the Open Console icon.
Select VUnit Console to open the VUnit Console View.
Since Sigasi Studio 4.14, the library configuration from run.py is used to configure the library configuration in the Sigasi Studio project.
Note that this automatic configuration does not work with linked folders.
You need to manually assign linked folders or any files/folders in them to a library.
Path separators in the run.py file need a /, also on Windows.
SystemVerilog
For SystemVerilog projects you need to manually add the VUnit include files to your projects:
Right click your project, select New > Folder > Advanced > Link to alternate location and add VUNIT/verilog/include as location.
Use the quick-fix on the failing `include "vunit_defines.svh" to add the include folder to the include paths.
Configure options for finding and running tests
In Window > Preferences > Sigasi > Toolchains > VUnit you can add different options for finding and running tests.
The Options for finding tests will be passed to run.py when generating the json file that lists the VUnit tests.
The Options for running tests will be passed to run.py when running the VUnit tests.
Select the Set VUnit output to project root to have the VUnit output stored in the project root instead of in the temp location from where VUnit is called.
Configuring the simulator
VUnit makes use of an external simulator to run tests. ActiveHDL,
RivieraPRO, GHDL, and ModelSim/QuestaSim are all supported. By
default, VUnit will try to find one of these simulators on your system
and will use the first one found.
If you want to use a particular simulator, you can set the
VUNIT_SIMULATOR environment variable to one of activehdl,
rivierapro, ghdl, or modelsim to specify which simulator to
use. In Linux, set the environment variable prior to starting Sigasi
Studio, either in your shell initialization scripts (e.g. .bashrc or
.bash_profile for bash shell), or set the variable on the fly in
your terminal window. In Windows, open the dialog Edit environment
variables for your account to set VUNIT_SIMULATOR.
You may also need to set the PATH of the simulator to use. For this
purpose, configure the appropriate environment variable for your
simulator with the correct path: VUNIT_ACTIVEHDL_PATH,
VUNIT_RIVIERAPRO_PATH, VUNIT_GHDL_PATH, or VUNIT_MODELSIM_PATH. For example:
Finally, it is also possible to configure the simulator in run.py,
as shown below.
# Some code omitted# Select simulator before calling VUnit.from_argv !os.environ["VUNIT_SIMULATOR"]="rivierapro"# Optionally set the PATH#os.environ["VUNIT_RIVIERAPRO_PATH"] = "/path/to/simulator/bin"vu=VUnit.from_argv()# More code omitted
For more information on simulator selection, check out the VUnit
website.
Run VUnit Tests
There are multiple ways to run VUnit tests in Sigasi Studio:
Right click your project and select Run VUnit tests to run all tests in your project.
Right click one or more HDL files and select Run VUnit tests to run all tests in the selected files.
Right click in the Sigasi editor and select Run VUnit tests to run all tests in the active editor.
Right click in the VUnit test name (the string in the run function call) and select Run VUnit test to run this single test only.
Rerun the tests in the VUnit view.
Inspect VUnit Test Results
When you run VUnit tests in Sigasi Studio, the VUnit view is opened. This view presents a convenient way to inspect the test results.
You can also open the Console View to inspect the entire VUnit output.
Handling specific common libraries
In Sigasi Studio, Common Libraries may be present in a project. Some
of these are standardized and available in all tools, e.g. IEEE VHDL
libraries, or the VUnit library in case of a VUnit project. Your
project may also require vendor or company specific common
libraries. External simulators, including the simulator which runs
your VUnit tests, require a particular setup to find your library.
If, for instance, ModelSim is used, then:
common libraries need to be pre-compiled,
a customized modelsim.ini with a reference to the pre-compiled libraries is required, and
VUnit needs to be aware of the customized modelsim.ini.
The latter is achieved by setting an environment variable
VUNIT_MODELSIM_INI which points at the customized
modelsim.ini. One could set this variable from the shell (Linux) or
user variables (Windows), but that is inconvenient as all projects
will use the same modelsim.ini. A better solution is to set
VUNIT_MODELSIM_INI in the run.py script, before calling
VUnit.from_argv().
# This is run.py# code omittedos.environ['VUNIT_MODELSIM_INI']='/path/to/custom/modelsim.ini'vu=VUnit.from_argv()# code omitted
Note that VUnit may still produce warnings that the library is
missing, as shown below. These warnings are harmless. They show up
because only Sigasi Studio and the simulator are aware of the library,
while VUnit is not.
WARNING - C:\Users\Wim Meeus\workspaceSigasi\VUnit-demo\design\design_top.vhd: failed to find library 'vucommon'
Alternatively, one could define the library and its
contents in the run.py script. In that case, VUnit will be aware of
the library and the warnings won’t show, but compile times will be
longer - which is exactly what common libraries are meant to avoid.
Using an external compiler in a VUnit project
If you want to configure an external compiler in a VUnit project
(e.g. for additional syntax checking), you need to ensure that the
compiler has the VUnit library. Otherwise, the compiler will flag all
VUnit constructs in your HDL code as errors.
How to compile and enable the VUnit library for an external compiler
is explained in the libraries section of this
manual.
The Sigasi Studio documentation generator makes the documentation process easier by automatically extracting information from your HDL source files. The biggest advantage is that there is only a single source for both your design and your documentation. While this gives no guarantee for the design staying in sync with the documentation, it certainly makes it easier.
The Sigasi documentation generator has following advantages:
No special coding requirements: the plain comments in your code are extracted for the documentation, no need for special annotations. Sigasi uses the same comment association as the hover provider. So to document a port, you append a comment to a port declaration. To document an architecture, you put the comment just on top of the architecture.
All included. All documentation processing is done in Sigasi/Eclipse. So you do not need to install extra tools.
Fully hyperlinked. If you export the documentation, you get a fully hyperlinked document.
Live preview: you can see what the documentation will look like while you type your code and comments.
Export Documentation
You can export documentation for the entire project or a specific toplevel by clicking the save icon on top of the Documentation View or via the Export… menu.
When you select the entire project, the design elements will be listed in alphabetical order.
When you select a specific toplevel, design elements will be ordered in a breadth-first order from the top down.
The resulting HTML file is saved in the sigasi-doc folder in the root of your project.
The generated Block and State Machine Diagrams are saved in subfolders of the sigasi-doc folder.
Sigasi Studio 4.5 introduced exporting the documentation to HTML.
You have to choose between Linked resources and Embedded resources when exporting the documentation.
Linked resources
Creates an HTML document with linked resources.
All Block Diagrams and State Machine Diagrams are in separate files which are linked from within the HTML document.
The custom CSS file, if present in the project root, will be referenced from the HTML document.
Embedded resources
Creates an HTML document with embedded resources. The documentation is in a single file.
The Block Diagrams and State Machine Diagrams are embedded in the HTML document.
The CSS from the custom CSS file, if present in the project root, will be included in the HTML <head>.
Any errors are logged to the console view.
Customization
Sigasi Studio 4.17 introduced pagination and the introduction and problems section.
Pagination
Enabling the Split pages by elements count will paginate the output documentation. This is useful for very big designs that produce documentation 100’s of MBs large.
The summary information about the design appears on the first page and fans out to subsequent pages that will contain the documentation about individual design elements.
Problems section
Enabling Include problem information will add a Problems section containing all the project’s Errors, Errors and warnings, or Errors, warnings, and infos. On top of that, the suppressed problems can also be shown.
Introduction section
If a sigasi-doc.md file is present in the root directory of your project, Sigasi will automatically include it in the exported documentation as an introductory chapter.
As usual with our documentation, this is a MarkDown file. This allows you to easily annotate the text.
The exported documentation includes the Dependency Diagram, State Machine and Block Diagrams.
If you created custom graphics configurations for one or more of your diagrams, these will be used instead of the default diagrams.
If you have multiple graphics configurations for the same diagrams, the alphabetically first one is used.
Custom CSS
If the root of your project contains a sigasi-doc.css file, this file will be used to style the generated HTML documentation.
Note that only the generated HTML will be affected and not the Documentation View.
For example, you can give the background and titles different colors. You can also change the font for the entire document or parts of it.
Entire sections for entities, architectures and modules can be given different background colors.
Likewise the list of processes can get a different background color.
The difference in documentation with the CSS settings described above is shown in the screenshots below.
Comment Association
Comments in HDL code are used to add extra information or documentation to that code.
Sigasi Studio uses certain rules to determine which comment belongs to which code.
This is important for documentation hovers, refactoring, formatting,…
Which comment belongs to which exact code is subjective.
Sigasi Studio associates comments with HDL declarations with following rules:
If there is a declaration before a comment in the same line (trailing comment), the comment is associated with this declaration. This comment can span multiple single line comments if they are aligned.
If there is no trailing comment and there is a comment with the same indentation on the line above the declaration, the comment is associated with this declaration. This comment can span multiple lines if all comments have the same indentation.
Empty lines break comment blocks
The association rules are illustrated in the image below:
The Formatter and Structural select respect (and fix) comments according to the association rules.
Special cases
VHDL components and component instantiations: If a component (or one of its ports or generics) does not have comment itself, Sigasi Studio will use the comment of the corresponding entity. This also works for component instantiations.
Comment markup with Markdown
VHDL and SystemVerilog comments are processed with a Markdown processor. This allows to add markup (e.g. bold, code, paragraphs, hyperlinks,…) to comments. This results in nicer hovers and documentation.
In hovers the complete Markdown syntax is supported. For documentation generation following features are supported:
paragraphs (add and empty comment line to break paragraphs)
line breaks (by adding two trailing spaces)
emphasis (*emphasis*)
strong (**strong**)
lists
tables (with alignment)
external links and email addresses (<https://www.sigasi.com>, [Sigasi](https://www.sigasi.com) and <sales@sigasi.com>)
Sigasi Studio 4.6 added support for Fenced Code blocks in comments.
This enables you to add text to the documentation without Markdown rendering.
To add a comment verbatim to the documentation, surround it with with triple back ticks: ```<verbatim comment>```
The BlockDiagram- and StateMachine views are a very useful way to explore and understand HDL designs, but sometimes that just doesn’t cut it.
The diagrams can be too complex and crowded to understand a design. For this reason, the diagrams can’t always be directly used in documentation. To solve this challenge you can make use of the Graphics Configuration Language.
The Language
The Graphics Configuration Language is a plain text file containing declarations and configurations, which when interpreted, result in grouping, filtering, and coloring in the diagram.
You can see it in action in the images below:
This BlockDiagram
Turns into:
This StateMachine
Turns into:
A plain text format was chosen over buttons and menus for several reasons:
It can easily be managed with your version control system because files can easily be compared and merged.
It’s easy to debug by yourself, unlike proprietary formats or UIs.
We can support you using all of our well-known features such as autocomplete, validations, formatting,…
It’s lightweight and can be used as the basis for the UI implementation.
Getting started
To get started, choose a design with a BlockDiagram or StateMachine you want to simplify.
Create a new Graphics Configuration file by going to File > New > Other > Graphics Configuration > Graphics Configuration File.
You can also press the Sigasi button on the top right of the BlockDiagram or StateMachine view.
From there, you can declare groups and configure your diagram, check it into version control, and share it with your colleagues.
Autocomplete (Ctrl+Space) helps you write most of the code while formatting (Shift+Ctrl+F) helps you to keep your file clean.
If you’re interested in the language’s exact syntax, you can find it here.
Features
The Graphics Configuration features:
Grouping
Hiding
Reassignment hiding
Block collapsing
Coloring
Regex matching
Note that in the BlockDiagram you can group blocks and wires while in the StateMachine you can only group states.
Graphics Configuration Editor features:
Autocomplete (Ctrl+Space)
Formatting (Shift+Ctrl+F)
Quick outline (Ctrl+O)
Show in BlockDiagram/StateMachine (Alt+Shift+W)
Navigate to declaration (Ctrl+click or F3 on identifier)
Double-click on a diagram element to navigate to it in the code
Hovering to show more information
Graphics Configuration for BlockDiagrams
You can express which diagram you want to filter in the first line of the file by writing diagram fullyQualifiedName. The fully qualified name in VHDL is always library.entity.architecture. In SystemVerilog, this is work.module.
E.g. if you want to filter the diagram for the architecture RTL implementing the entity ent in the work library, you use the following line as the first line: diagram work.VME64xCore_Top.RTL.
The file is read from bottom to top. You start with the above definition of the diagram, then within that, you can hide reassignments, create groups and finally, create configurations for ports, blocks, and edges.
Hiding reassignments
When using a lot of reassignments or when you’re indexing vectors, you can get a skyscraper effect in the generated block diagrams.
By using reassignments hide you can draw through the assignment blocks making the diagram a lot simpler.
Skyscraper
Hidden reassignments
Multiple reassignments
Hidden reassignments
Grouping
After hiding the reassignments you can define groups of edges or blocks.
The syntax for a group is as follows: def Type group ID (Identifiers)
Where Type is block or wire, ID is the new name of the group and Identifiers is a comma-separated list of existing IDs (Graphics Configuration, VHDL or SystemVerilog) or a regex.
The syntax for a regex is regex"regex_pattern". This uses Java regexes, you can also find a cheat sheet here.
You can also check what the regex matches by hovering over the query.
E.g. if you want to group block2 and block3 you can add either of the following lines: group block middle regex"block[23]" group block middle (block2, block3)
Ungrouped
Grouped
The same can be done for wires by using wire instead of block.
Ports can be grouped by grouping the wires attached to the ports into a bus.
Configuration
The syntax for a configuration block is as follows: Type Identifiers { ConfigurationItem* }
Where Type is block, wire, or port.
The syntax for a ConfigurationItem is as follows: hide | collapse | color GraphicsColor | reassignments hide
You can discover which colors are available here or through the autocomplete.
E.g. we can color a block, called middle, green and hide its internals: Colored and collapsed group
Configurations are not cascading (unlike CSS).
Coloring the middle block green does not turn all its internal blocks green as well.
Note that the language can not see everything: it can not see blocks, wires, or ports that are within another block.
E.g. we can’t type block block3 { color red } as block3 is part of the block middle.
To access a block within a block, we have to nest configurations.
Nested configuration
Another use case would be to hide (unconnected) ports by using port a { hide }.
Hidden port
Note that when you hide a block or port, the edges that are connected to them will also be hidden.
It is also possible to hide reassignments in configurations, as you saw in the above skyscraper example, the reassignment in the generate block was not hidden.
You can do so as follows:
Hidden reassignment in generate
Graphics Configuration for StateMachines
StateMachines are configured in the same way as the above BlockDiagrams, except the only Type that can be used is state.
The header is also slightly different, the syntax is as follows: statemachine architecture : state_variable.
For an example, you can check out step_3_state_machines.vhd (in our VHDL Tutorial) with this filter file.
Hiding labels
Labels on state transitions can be hidden using labels hide.
You can also use labels comment or labels condition to only show comment or condition labels on the state transitions.
Since Sigasi Studio is built on Eclipse, you can install third-party Eclipse plugins.
The best place to start looking for a plugin is the Eclipse Marketplace. We list some interesting
plugins here. Since these are third-party plugins, there is no official
support from Sigasi.
Installing Plugins
Unlike most Eclipse distributions Sigasi Studio is shipped without the Eclipse Marketplace plugin and the standard Eclipse update sites.
Hence, you have to add a plugin update site to install new plugins.
Click Help > Install New Software Now click Add and fill out the update site. Press OK to confirm.
Installing
Still in the Install dialog, search for the plugin you want to install. You can browse the list of available plugins or use the filter text above the list of plugins.
Select the checkbox for the plugin and click Next
Follow the instructions for the rest of the wizard.
Revision Control Systems
Sigasi Studio supports a wide range of Revision Control
Systems (also known as
Version Control or Source Control systems). Support for revision control
is based on Eclipse plugins. This section contains a preliminary listing
of the most popular revision control systems.
GIT
Recommended plugin: EGit
This plugin is shipped with the standalone version of Sigasi Studio.
While this is not strictly speaking a version control system, Sigasi Studio has
a built-in feature that keeps a local history of your files.
Learn more.
Other Systems
Some other popular revision control systems include:
Python: You can add support for Python to Sigasi Studio by installing the PyDev Eclipse plugin.
Use https://www.pydev.org/updates as update site.
Remote Collaboration
You can use the Saros plugin to remotely collaborate on the same project with multiple people. You’ll see edits from collaborators in your own editor as they happen. To install the Saros plugin in Sigasi Studio, use https://www.saros-project.org/update-site/eclipse as update site.
Opening to a Shell
If you want a quick way to open files and folders from the Project Explorer in a terminal, EasyShell is a useful plugin.
If the user interface of Sigasi Studio is unresponsive, you can interrupt the internal compilation process by pressing the stop button in the progress view. To activate the progress view, select Window > Show View > Other… > General > Progress, or click the tiny conveyor belt icon , on the right side of the status bar.
Create performance and memory snapshots
Performace snapshot
Sigasi Studio has a built-in profiler. By default this profiler is not active.
On some occasions we’ll ask you to provide an anonymized performance snapshot from the profiler.
To obtain this snapshot, follow the steps below.
Activate the profile using Help > Sigasi > Performance > Start Async Sampling
On Windows, use Help > Sigasi > Performance > Start Sampling instead.
Perform the laggy operations in Sigasi Studio
Stop the profiler using Help > Sigasi > Performance > Stop Profiling
Memory snapshot
It may happen that, as part of a support case, we’ll ask you to
provide an anonymized memory snapshot of a running Sigasi application.
To obtain this snapshot, select Help > Sigasi > Performance >
Capture Heap . You’ll be prompted for a location and a filename to
store the memory snapshot.
Sending your snapshot to Sigasi
The snapshot you’ve obtained needs to be obfuscated to anonymize it and it needs to be uploaded.
For this a snapshot_anonymizer script is provided in the Sigasi Studio installation folder.
You can verify the obfuscation first before sending the uploading the snapshot to us.
Sigasi support will provide instructions for uploading the snapshot.
The editor displays old contents of a file
If you edit a file outside of Sigasi Studio with an external editor, Sigasi Studio will normally notice the changes and ask if you want to load the changes. If
it doesn’t, you can refresh the editor’s content by pressing F5 or by right-clicking a file or a project in the project explorer and
selecting Refresh.
No content in the editor and only a cross in the editor tab
If you see empty views in Sigasi Studio on Linux: make sure libXss or libXscrnSaver is installed.
Hover makes the editor hang for ~10s
If you experience hangs when hovering over identifiers in Sigasi Studio on Linux: make sure webkit2gtk4.0 is installed.
How much local history will be stored?
Sigasi Studio stores the history of your file so that you can compare your current version with the version you saved an hour ago.
You can define how much disk space is used for storing local history in Windows > Preferences, select General > Workspace > Local History.
For more information on local history, check out this page.
I see hundreds or thousands of errors
If you see a large number of errors, you either have very, very buggy code (not so likely) or your project is not configured correctly.
Check that all files are mapped to the correct library.
Check that all stale files are ignored. (see the section on unneeded files)
Check that all third party libraries are included.
Make sure that automatic build is enabled.
Auto Build is not Enabled
Symptoms:
When you introduce an error in a VHDL or Verilog file and save the file, an error marker shows up in the file, but not in the problems view.
Navigation (Find References, Open Declaration) behaves strangely when it involves more than one file.
Other features that involve multiple files behave incorrectly: autcomplete, refactoring, …
VHDL files contain errors, but these errors do not show up in the Problems View.
Cannot select a top level in the Hierarchy View
Cannot navigate from a name in one file to its declaration in another file.
In the Project Explorer, the name of the library (for example: [work]) is not shown next to the filename.
Cause: The project does not have VHDL support enabled
Resolution: Enable VHDL support: right-click the project > Configure > Add VHDL support
Project does not have Library Mapping Information
Symptoms:
All VHDL-files in the project are not mapped
The Project contains only one error: “This VHDL project can not be built since the library mapping information is missing”
VHDL files contain errors, but these errors do not show up in the Problems View.
In the Project Explorer, the name of the library (for example: [work]) is not shown next to the filename.
Cause: The project does not have a (valid) VHDL library mapping information file
Resolution: Reset the library mapping: right-click the project > Library Mapping > Reset Library Mapping
Project does not have Common Libraries
Symptoms:
Project has many errors, in practically all files. Project build may be slow.
The standard data types (like integer and std_logic) are not recognized.
The IEEE and STD libraries are not recognized.
The IEEE and STD files are either missing or are mapped to the wrong library (for example: [work]).
Cause: Common libraries are not configured correctly.
Resolution: Reset the common libraries: right-click the project > Library Mapping > Reset Library Mapping
Sigasi Studio analyzes HDL files that I do not need
By default, Sigasi Studio assumes that all VHDL or Verilog files are part of the project. However, some projects may contain multiple files with older or alternative definitions of a VHDL object. We call these stale files, because they are no longer used. In such a case you will want Sigasi Studio to ignore certain files.
Ignored resources are decorated with a icon in the project explorer view.
Sigasi Studio startup fails: “Could not create the Java virtual machine”
On some computers, the standalone version of Sigasi Studio will fail to start with an error message similar to: “Could not create the Java virtual machine.” This happens especially on 32-bit Windows machines with less than 2GB of physical memory. The reason is that the Java virtual machine tries to allocate more memory than what is available.
In order to solve this, you can decrease the default heap size settings. You can do this by adding following lines to sigasi.ini or eclipse.ini in your Sigasi Studio installation folder:
-vmargs
-Xmx1000m
This sets the maximum heap size to 1000 MB (instead of the standard 3GB).
Note: Do not use eclipsec.exe, as this will ignore all of the settings configured in the eclipse.ini file.
Sigasi Studio shows a startup message about port 4444 already being in use
If you want to run Sigasi Studio on a server with multiple users, the configuration files should be updated according to the descriptions here.
I want a clean restart
If you ever suspect that the state of your project is inconsistent in Sigasi Studio, you can do one or all of the following things. Consider these
steps to be advanced usage; you should not need them during normal operation.
Force a clean compilation
You can force a completely clean compilation by selecting: Project > Clean … > Clean All Projects > OK.
Remove stale markers
Sometimes markers remain visible, even after the problem is fixed or when a file is excluded from compilation. We call these stale markers and they are can be caused by a crash during compilation.
You can delete these stale markers from the Problems View: In the Problems View, select the markers and press DEL (or right-click and select Delete).
Note that during the next build, the tool may generate new markers. If you want to suppress certain warnings, you can configure the linting rules.
Remove the cache
For faster performance Sigasi Studio is using a cache.
Sometimes the cache can get corrupted which might cause internal errors.
The cache is located in your workspace.
By default, Sigasi Studio’s workspace is located in ${HOME}/workspaceSigasi.
To remove the cache, stop Sigasi Studio and delete the folder workspaceSigasi/.metadata/.plugins/com.sigasi.hdt.shared.ui/resource.cache/sigasiBuildCache.
Remove the workspace state
Much of your configuration and cached data is stored in your workspace.
By default, Sigasi Studio’s workspace is located in ${HOME}/workspaceSigasi.
A lot of this data is stored in the hidden .metadata directory.
Sometimes, a part of your metadata can become corrupt.
It can help to remove the .metadata directory (take a backup first!).
This clears all of your workspace state.
You will need to enter your license code again.
You will need to import your projects again. Import > General > Existing Projects into Workspace
Keep getting reports about an “Incompatible version of Quartus”
If you are using the integration with Intel Quartus. Some people keep getting a dialog box that says something like:
Incompatible version of Quartus
Project interface was created with an older, incompatible version of Quartus.
Is it OK to upgrade the project to match the installed version of Quartus?
Obviously, you should upgrade the project. If this message keeps popping up, you may want to check that Sigasi Studio is using the correct version of Quartus, in the Sigasi Studio application: Window > Preferences > Sigasi > Toolchains > Intel Quartus.
Contact support
If this troubleshooting guide did not solve your problem, please send us an email
.
Any of the following information will help us help you:
Steps to reproduce your problem
Description of the expected behavior and the actual behavior.
The version number of your Sigasi Studio: Help > About Sigasi > Installation details Note that the version number contains the date of the release. (For example, version 2.0.1.20110809… was released on August 9, 2011.)
As you become more experienced with Sigasi Studio, you will find that there are a number of actions that you perform quite often. At some point, you may feel that the GUI-based approach becomes too slow for these actions. For that reason, Sigasi Studio provides a number of keyboard shortcuts. They are a great way to boost your productivity. A printable cheat sheet with all shortcuts on one page is available for download.
In this chapter, we describe the available keyboard shortcuts.
Top keyboard shortcuts
In this section, we list the most important shortcuts.
Open Resource (Shift+Ctrl+R): Shift+Ctrl+R opens a dialog that allows you to swiftly open an editor on any file in the workspace.
Open Declaration (F3):
Use F3 to navigate to the declaration of the selected identifier.
Open Design Unit (Shift+Ctrl+D): Shift+Ctrl+D opens a dialog in which you can type a name or pattern to open a specific VHDL or SystemVerilog design unit name.
Backward History (Alt+Left):
Often, when you navigate to a declaration you want to go back to where you came from; just press Alt+Left.
Content Assist (Ctrl+Space):
With content assist (autocomplete) you can really speed up coding VHDL. Just press Ctrl+Space to get a suggestion of possible autocompletes in the current context.
Go to next marker (Ctrl+.)
Does your file contain warnings or errors? Quickly navigate to the next problem by pressing Ctrl+. (Ctrl+, jumps to the previous problem).
Quick Fix (Ctrl+1):
To fix problems even quicker, navigate to the problem with the previous shortcut. Press Ctrl+1 to activate the Quick Fix, select the fix with the UP or DOWN keys and execute the Quick Fix with Enter.
Go to Line (Ctrl+L)
You can directly jump to a certain line with this shortcut. You can display the line numbers by right-clicking on on the gray bar on the left side of the editor view and clicking on Show Line Numbers.
Search references (Shift+Ctrl+G)
To search for all occurrences of a given identifier, just select the identifier and press Shift+Ctrl+G. The search view is displayed, with a match for each occurrence (possibly in multiple files)
Rename Refactoring (Shift+Alt+R)
Once you get used to the rename refactoring you will be using it all the time. Use Shift+Alt+R to run it even quicker.
Toggle Block Selection (Shift+Alt+A)
Switch between regular and block selection mode.
Structured Select (Shift+Alt+Up/Down/Left/Right)
Select VHDL or Verilog code, based on its syntactic structure. (Structured selection)
Format (Shift+Ctrl+F)
Format your current VHDL or SystemVerilog file.
Quick Access (Ctrl+3, This is the shortcut to use, when you forgot the shortcut you actually need.)
With Quick Access you can quickly find open editors, available perspectives, views, preferences, wizards, commands, etc. Simply start typing the name of the item you wish to invoke.
If you are using MacOS, most of these keyboard shortcuts use Command instead of Ctrl. To inspect the exact list of keyboard shortcuts, go to Preferences > General > Keys.
Customizing keyboard shortcuts
Keyboard shortcuts can be easily customized via Preferences > General > Keys.
This preference page also enables you to select the Emacs scheme, for more Emacs-like keyboard shortcuts, or (if you have installed the UltraEdit key bindings for Eclipse plugin) the UltraEdit key bindings.
If you’re looking for Vi or Emacs keybindings, have a look at Third Party Plugins.
The advanced setup of Sigasi Studio is meant for engineers and organizations who want to:
automate the setup of Sigasi Studio
automate the setup of a project (or a set of related projects)
combine Sigasi’s VHDL and SystemVerilog support with other programming languages, version control settings, or different Eclipse plugins
ensure that all team members share the same settings (indent style, templates, linting preferences…).
The advanced setup uses
Oomph, a highly
customizable installer for Eclipse. Oomph is configured with setup
files. Most of the team members will use these files when setting up a
new version of eclipse and/or when they join a new project. Only every
now and then, e.g. at the start of a new project, a setup file needs
to be created or updated.
For the standard setup procedure for Sigasi Studio, look here.
The user perspective: using existing setup files.
Setting up the latest version of Eclipse with the Sigasi Studio plugin
is easy and straightforward. One or two files are needed:
The product setup file determines the Eclipse setup, e.g. plugins and workspace settings.
The optional project setup file tells Eclipse how to set up a project, e.g. from a version control system.
To get the installation started, download, unzip and run the Eclipse
installer. In the top-right
corner, click the 3 horizontal bars (the burger menu) and select
Advanced Mode….
Next, click on the plus icon next to the filter text and enter the URI
of the product setup file. This can be a file on your system or a web
link, e.g. to a file on your team’s internal web page. For demo
purposes, you can use our example file:
https://insights.sigasi.com/resources/manual/SigasiStudio.setup. Click
OK to close the pop-up.
Select the desired product setup under User Products and click Next >.
Now you can optionally select a project to set up. Again, click the
plus icon next to the filter text and enter the URI of the project
setup file. You may want to try our demo project from
https://insights.sigasi.com/resources/manual/SigasiDemoProject.setup
which will set up a Sigasi project using git version control. Select
the desired project (checkbox) and click Next >.
Next, configure the path for your Eclipse installation, workspace and
project. Check Show all variables to see all relevant paths. Make
changes if required and click Next > to continue. In the next
screen, click Finish to start the setup process.
At the end of the product setup (Eclipse install), Eclipse starts
up. If a project setup was selected, a second Eclipse installer starts
for that purpose. When finished, the Eclipse installer window(s) may
be closed by clicking Finish.
Your new Eclipse with Sigasi Studio is now ready, with the optional
project if one was selected.
Setting up the setup files
So far, we’ve seen how a user can set up Eclipse, Sigasi Studio and
projects quickly and easily using setup files. These setup files are
convenient for teams to keep tool settings consistent between team
members.
This section discusses how to create and modify setup files. Setup
files use the XML format, which means that they are structured text
files and therefore human readable. The Eclipse Oomph plugin has a
convenient graphical editor for these files. Using a text editor is
error-prone and therefore not recommended.
Setting up Eclipse Oomph
Oomph is an Eclipse plugin, so you’ll want to either run Oomph in your
current Eclipse, or install a separate (minimal) Eclipse. The Eclipse
installer can be found
here. Recent versions of Eclipse
contain Oomph by default, so you shouldn’t need to install anything
extra.
If your Eclipse doesn’t contain Oomph, open Eclipse, go to Help >
Install New Software…, enter
http://download.eclipse.org/oomph/updates/release in the box next
to Work with, select the Oomph Setup > Oomph Setup and proceed
with the installation.
Then, create a new General project to contain the setup files:
File > New > Project… > General > Project, name the project and
click Finish.
Now you can either create new product and project setup files in this
project, or copy (drag & drop or otherwise) files into the project for
customization.
Product setup file
For a product setup file, it is recommended to start from one of our
examples: either a fairly minimal
SigasiStudio.setup or an
example in which a few extra workspace options are configured:
SigasiStudioPlus.setup.
Place one of these files in your Oomph project and open it for further
customization.
If you prefer to start from scratch, right-click your Oomph project
and select New > Other… > Oomph > Setup Product Model, and check
out one of the above examples for the basic configuration.
Both examples will install Eclipse with Sigasi Studio and Git revision
control. The minimal example will, in addition, configure the maximum
heap space for Eclipse, it will enable the Sigasi perspective, and it
will turn off the Preferences Recorder. The extended example, shown
above in the Oomph editor, contains further options for linting
severities, formatting options and an autocomplete template.
Note the three groups of settings:
Eclipse Ini: settings that will go in eclipse.ini.
P2 Director: plugins to install and the repositories where they
can be found. Here you can add additional plugins, e.g. to support
an additional programming language or a different revision control
system. To add an item, right-click P2 Director, and select
New Child > Requirement for an additional plugin, and
subsequently New Child > Repository for the plugin repository.
Custom preferences: workspace settings. Here you can fine-tune
workspace settings to the need of your team. To add a new
preference, first find the key and the value of the preference
which you want to configure (see below). Then, right-click Custom
preferences and select New Child > Preference. Then fill out
the key, the value and the optional description.
Finding keys and values of workspace preferences is easy as
follows. First, install a custom Eclipse with the setup file as it is,
i.e. without the preference. In that copy of Eclipse, select
Window > Preferences > Oomph > Setup Tasks > Preference Recorder, check the
Record into: checkbox and click the Open the recorder target
file icon on the same line. Then, set other preferences as
desired. After clicking Apply and Close, a pop-up like the one
below shows the information for the key and value to configure.
After adding the desired preferences and plugins, it’s time to save
the setup file and use it with the Eclipse installer, as described
here.
Project setup file
For a project setup file, it is recommended to start from our example:
SigasiDemoProject.setup,
which you can copy into your Oomph project and open for further
customization. If you prefer to start from scratch, right-click your
Oomph project and select New > Other… > Oomph > Setup Project
Model, and check out the above example for the basic configuration.
Specify the location of your project and save the file. Now it is ready
for use in the Eclipse installer.
We recommend to save project preferences in version control with
the project, rather than in a project setup file. That way, changes to
project settings get propagated to all team members effortlessly, and
each revision of the project contains matching project settings. To
that end, store .project, .library_mapping.xml and .settings of
your project in version control.
Sigasi Studio supports VHDL versions 1993, 2002, 2008, and 2019 as well as Verilog (2005) and SystemVerilog (2012).
You can select the default VHDL version to use in Window > Preferences > Sigasi > VHDL.
You can set the default Verilog/SystemVerilog version in Window > Preferences > Sigasi > Verilog/SystemVerilog.
Since Sigasi Studio 3.2, you can also set the language version
per project, folder, and file.
In the Project Explorer, right-click your project, folder, or file; select Properties > VHDL Version
or Properties > (System)Verilog Version and select the version via the dropdown menu.
When you change the language version of a file, only that file is affected.
However, when you change the version of a folder, then everything in that folder will have the new language version.
Any overrides in the folder and its sub-folders will be removed.
When you are defining the language versions for a new project you should map from top (project root) to bottom (files).
The version information is stored in <project path>/.settings/com.sigasi.hdt.vhdl.version.prefs and <project path>/.settings/com.sigasi.hdt.verilog.version.prefs.
We recommend you add this file to version control so you can share it with your team.
Notes:
VHDL libaries: Any new project that you create will have the Common Libraries (STD and IEEE) that correspond to your selected VHDL version.
Your existing project will not be modified.
If you want to update the Common Libraries for an existing project, right-click the project and select Library Mapping > Reset Common Libraries.
Since Sigasi Studio 3.3, you will get a warning if your Common Libraries do not match the VHDL version of your VHDL file.
You can use the proposed quick fix to resolve the issue.
If you want to compile VHDL 87 code, you should select the “1993” option. There are no checks to warn about constructs that were not supported in 1987, but that were introduced in 1993.
Sigasi Studio does not send the Common Libraries to an external compiler. It is expected that these libraries are pre-compiled.
Colors and Fonts
You can configure the code coloring by selecting Window > Preferences > Sigasi > VHDL > Syntax Coloring.
For each class of semantic and syntactic elements, you can select the font, letter color, background color and style (bold, italic, underline, strike through).
Font Size
Sometimes you want extra small fonts such that you can fit more content on your screen. Other times you
may want extra large fonts such that you can use a beamer and your audience can see what you are doing.
Most fonts, including the font that is used by the editors, can be controlled in the preferences:
Window > Preferences. Fonts are controlled in General > Appearance > Colors and Fonts. The font of the editors is configured in Basic > Text font.
Some fonts cannot be controlled from this preference page. These fonts are defined by general system settings and are used for displayiing the menu names, the Project Explorer View, and the Outline and Hierarchy Views. On
Windows, you can change these fonts by changing your font settings in the Windows Control Panel. On Linux, these fonts are controlled by a settings file: ${HOME}/.gtkrc-2.0. You can change the font by adding a line like:
gtk-font-name = "Sans 10"
You have to restart Sigasi Studio before these changes take effect.
Annotations Colors
Annotations are colors added on top of your text editor, and to the right of your text editor, in the scroll bar. The image below shows annotations for each occurrence of a certain data type. The color has
been changed to bright green.
You can change the color of annotations in Window > Preferences > General > Editors > Text Editors > Annotations.
For the particular case of occurrence annotations, you want to modify the color for annotation type Occurrences.
If more than one Occurrences type is displayed, you need the org.eclipse.xtext.ui.editor.defaultOccurrenceAnnotation.
The others may refer to occurrences for Java or other plug-ins.
Tabs and Spaces
If you want to use spaces instead of tabs, you can set your indentation preferences in Window > Preferences > General > Editors > Text Editors. Here you can select choose to Insert Spaces for Tabs and choose your preferred Displayed Tab Width.
The “Gutter”
The Gutter is the small area to the left of the editor view. It is used for displaying extra information about your code.
Line numbers: What line is this?
Quick Diff: Did this file change?
Folding: hiding pieces of code from view
Markers: error markers, warnings, and bookmarks.
There is not much to configure about markers, but the other categories can be turned on or off.
Line Numbers
To enable line numbers, right-click in the gutter and select Show Line Numbers.
Quick Diff
Instead of using a compare editor, you can enable quick diff support and see the changes within the text editor. This feature can be enabled via Window > Preferences > General > Editors > Text Editors > Quick Diff.
When you enable Quick Diff, you can see changes in the active editor with the version on disk (or the latest version in version control), by hovering the annotations in the gutter.
You can choose the severity of linting rules in Window > Preferences > Sigasi > VHDL > Errors/Warnings.
Read more information about Linting and Quick Fixes.
Language
Eclipse is available in several languages, and you can install the language pack of your choice. Read more in this support article: Installing translations for Eclipse
Keyboard Shortcuts
Sigasi Studio comes with a large number of Keyboard Shortcuts preconfigured. You can configure keyboard shortcuts (key bindings) in Window > Preferences > General > Keys. You can modify individual keyboard shortcuts or add new key bindings.
There is also a preconfigured scheme for Emacs-like keyboard shortcuts.
After you have configured your keyboard shortcuts, you can export your settings and share them with your colleagues (or re-import them on another computer):
To export, go to File > Export… > General > Preferences, and select Key Preferences. To import that file: File > Import… > General > Preferences.
Sigasi Studio’s license key management system is based on the well known FlexNet (a.k.a. FlexLM) license manager.
Sigasi Studio supports both node-locked and floating license keys.
The Sigasi Studio edition is controlled by the license key.
This page explains how to configure your Sigasi license in Sigasi Studio on Eclipse.
There is a separate page documenting License Server Management.
Node locked licenses
If you have a node-locked license, you can enter your license key directly in Sigasi Studio.
Open the Sigasi Studio License Key preference page: Window > Preferences > Sigasi > License Key
Click Edit License File
paste your key in the dialog
An example node-locked license looks like this. Note that the first line starts with INCREMENT
Configuring Floating license in Sigasi Studio (FlexNet Client)
In order to use a floating license, Sigasi Studio needs to know how to contact the server.
The license server can be configured in Sigasi Studio or using an environment variable.
Configure the license server in Sigasi Studio
In Sigasi Studio, navigate to the License Key preference page via:
Window > Preferences > Sigasi > License Key.
Next enter <portnumber>@<servername> in the License key path. For example:
27000@myserver.example.com
If you have redundant license servers, enter each of the license servers separated using “,”.
It is recommended to specify the primary server first in the list.
For example:
If you have multiple, non-redundant license servers, the servers should be separated using “:” on Linux and using “;” on Windows.
If you leave the License key path empty, Sigasi Studio will try to use an environment variable
to find the license server.
Configure the license server in an environment variable
You can also set your license server via an environment variable instead of configuring it in Sigasi Studio.
Both SIGASI_LM_LICENSE_FILE and LM_LICENSE_FILE are supported.
When SIGASI_LM_LICENSE_FILE is set, LM_LICENSE_FILE is ignored.
Note that if you want to use an environment variable, you can not enter a path in the License Key preference page.
The value on the License Key preference page has priority over environment variables.
You can release a floating license (check a license in) without closing your Sigasi Studio application or Eclipse application. This is useful if you use Eclipse to edit other files than VHDL files, like C or Tcl.
First, make sure that all VHDL and Verilog files are closed and all VHDL and Verilog projects are closed. Next select Help > Sigasi > Floating license > Release Sigasi Floating Licenses
To get the license back (to check the license out), open the license dialog Help > Sigasi > Configure License… and press Apply.
How to block Sigasi Studio from checking out a license?
If you have configured an environment variable with the location of a FlexNet license server, you can instruct Sigasi Studio not to check out a license by setting the Sigasi Studio License key to none.
Checking out and releasing the XPRT license
If you have a license for Sigasi Studio XPRT
, this is actually licensed as a com.sigasi.hdt.xl FlexNet feature
combined with a com.sigasi.hdt.xl.doc FlexNet feature.
The XL license is checked out as described above.
The XPRT license is checked out automatically in the following cases:
When you open the Block Diagram view
When you open the State Machine view
When you open the Class Hierarchy view
When you open the VUnit view
When you export documentation
When you click Help > Sigasi > Floating License > Check out Sigasi Studio XPRT license
The XPRT license can be released via: Help > Sigasi > Floating license > Release Sigasi Studio XPRT Floating Licenses.
Available in Sigasi Studio from version 3.1 to 4.17.2.
OneSpin integration is no longer available in Sigasi Studio 5.0 and
above. If you require OneSpin integration, you can keep using
Sigasi Studio 4.17. Please also get in touch with Sigasi
support to discuss your needs.
OneSpin Setup
Before you can run OneSpin as external tool in Sigasi Studio, it needs to be correctly set up.
Make sure the environment variable ONESPINROOT is set, and points to the root folder of your OneSpin installation
Make sure the FlexNet environment variable OSSLMGR_LICENSE_FILE is set, and points to a valid OneSpin License server.
Running OneSpin in Sigasi Studio
If the ONESPINROOT environment variable is set, OneSpin will be available on the Sigasi > Toolchains Preference page.
Attention: OneSpin in Sigasi Studio does not support project names with spaces.
Once OneSpin is selected as external compiler, Sigasi Studio will automatically run read_vhdl and read_verilog on your HDL source files. All OneSpin output will logged to the Console View. All warnings and errors will be shown as problem markers in the Sigasi Studio editor.
Consistency checks
You can also run the OneSpin Consistency Checks on your design:
Set the toplevel in the Hierarchy View (Set Top). VHDL entities and Verilog modules are supported as toplevel. Please contact us if you need support for VHDL architectures as toplevel.
Run OneSpin by clicking the OneSpin icon in the Hierarchy View
All OneSpin output will logged to a new tab in the Console View. All warnings and errors will be shown as problem markers in the Sigasi Studio editor.
Running the OneSpin Consistency Checks can be a long process. It can be canceled by clicking the stop button in the Progress View.
This page explains how to install and configure the Sigasi Studio extension for VS Code.
Requirements
VS Code Version
The extension requires VS Code or VS Codium version 1.77.0 or higher.
Java Runtime
The path to use the Java Runtime (JRE) can optionally be configured in the settings.
If the setting is empty, the extension will extract the included JRE in the user’s home folder.
To install the extension, open the Extensions pane using Ctrl+Shift+X.
In the Search field on top, type Sigasi.
Click the Sigasi extension and click Install.
The settings for the Sigasi extension can be reached trough:
Open the Command Palette using Ctrl+Shift+P
Start typing and select Preferences: Open Settings (UI)
In the Search field on top, type Sigasi.
First, configure the Path To License. This can be a local node-locked license file or a floating license server (e.g. 27000@myserver.example.com). The setting for the license path is similar to the one in Sigasi Studio on Eclipse.
Optionally, configure the JRE location in Sigasi > Java: Path. Make sure to add the java executable name in the configured value.
Alternatively, the Sigasi extension settings can be accessed through the Manage icon () in the extensions overview.
Talkback
You can help improve the Sigasi extension for VS Code by enabling the automatic submission of usage statistics and error stack traces.
More information about this feature is available on the Talkback manual page.
This feature is disabled by default.
To enable talkback in the VS Code extension, open the settings and enable the Sigasi: Enable Talkback option.
The messages sent to Sigasi can also be logged locally. Then you can view these messages using the Sigasi: Open Talkback Log command.
In order to log the messages locally, a data storage needs to be configured.
On Disk Caching
You can specify a directory to be used by the Sigasi Language Server to write the cache and talkback logs to.
Open the settings and search for Sigasi › Server > Caching: Data Location.
The directory needs to exist already.
Choose a local folder for optimal performance.
Once you’ve configured this directory, the setting Sigasi > Server > Caching: Enable On Disk Caching can be enabled.
The cache will speed up the plugin by preserving the state from an earlier moment.
This will speed up the build significantly.
Be careful though: opening the same project in another VS Code window at the same time will corrupt the cache causing a myriad of issues.
The extension will start once a .project file is detected in the root of the open folder.
The project settings and library mappings are compatible with SiStE
.
See the Setting Up a Project and Libraries manual pages for all details.
If you’re familiar with Eclipse Resource Filters, note that these are not supported by VS Code and will be ignored if there are any filters in the .project file extension.
To change library mappings, you can use the right-click menu in the Project View and select Set Library as shown in the image below.
Then you can select an existing library or choose New Library… to type a new library name.
Once you type a new library name, the file/folder you selected will be added to the library you created.
If you want to add a file/folder to an existing library, you can choose one of the existing ones from the list (such as work).
If you want to exclude files/folders from a Sigasi project, select Exclude from Build. When you do this, that file or folder (along with its contents) will no longer be used in your project.
Note that the excluded resource(s) will still be visible in the Project View and you can still add them (Set Library) to the project.
Creating new libraries, adding a file/folder to an existing library, or excluding files/folders from build will modify the .library_mapping.xml file in your project.
VHDL and Verilog Version
To change the VHDL or Verilog version, you can right-click on a project, folder, or file in the Sigasi Project View and click Set Language Version.
Then select whether you want to set the VHDL or Verilog version. If you only see one of the two, you might need to add language support. Finally, select the version you want.
Language Support
To add or remove language support, you can right-click on a project from the Sigasi Project View, click Configure, and Add/Remove VHDL or Verilog/SystemVerilog Support. This will enable or disable language preferences among others.
Workspace
To add a new project to your workspace, press File > Add Folder To Workspace.
Make sure the project you’re adding has a valid .project file.
Environment Variables
Sigasi Studio supports environment variables in its project configuration.
This helps to avoid absolute paths in the .project file.
To use environment variables, you have to prefix the environment variable with ENV-.
For example: to refer to the home directory you can use ENV-HOME.
Custom Project Variables
Some variables are automatically defined.
PROJECT_LOC with the PATH of your project
PARENT-<COUNT>-<VARIABLE> which points to COUNT levels above the PATH of the VARIABLE
For example, if your project lives in /design/projects/project1, then PARENT-2-PROJECT_LOC/companylibrary points to /design/companylibrary.
You can also use custom project variables, e.g. VUNIT to point at your VUnit installation.
You can configure these variables as follows:
Press Ctrl+Shift+P to open the Command Palette
Select Preferences: Open Settings (UI)
In the Setting tab, navigate to Extensions > Sigasi > General > Custom Project Variables
Add variables and their values as required
Note that custom project variables can be set on the User level, and also per Remote or for a specific Workspace.
This page documents the Views added to VS Code by the Sigasi extension.
Project View
The Project View offers a file browser for your projects in which external folders that are not physically part of your project can exist.
This can be useful for including external IP in your projects.
The project view also offers a lot of custom Sigasi functionality e.g. library mapping, version setting, preference view, …
Linked Libraries
Any (external) libraries and files, that are not within the folder of the opened project, can be added using the Project View.
In the Project View, right-click any file or folder and select the New Linked File… or New Linked Folder… option to add files and folders from outside the project location.
The configuration of the external files and folders will be kept in the .project file in the project root.
External files and folders can be added anywhere in the project.
If you add a large folder (e.g. the unisim primitives), make sure to exclude the folder (Right-click > Set Library > Exclude from Build) from being build and only include the required files.
Or just put the library files in a folder called Common Libraries.
Then they will only be indexed and not analyzed for errors.
Buttons in the Project View
These buttons are available in the Project View.
Create a new file
Create a new folder
Refresh the Project View
Toggle linking the Project View with the editor
Collapse all folders in the Project View
Hierarchy View
Initially, the Hierarchy View will be empty.
To use the Hierarchy View, right-click an entity, architecture, or module name in the editor and select Set as Top Level from the pop-up menu.
This will populate the Hierarchy View with the structure of the top level.
As you make changes to the design, the Hierarchy View will not automatically refresh.
To refresh the Hierarchy View, use the refresh button (
).
If you want the selection in the Hierarchy View to follow your position in the editor, make sure to enable the link with editor button (
).
Buttons in the Hierarchy View
These buttons are available in the Hierarchy View.
Expand the full hierarchy
Toggle link with the editor
Toggle showing only instantiations
Refresh the Hierarchy View
Collapse the hierarchy
Preferences View
To open the Preferences View, right-click the resource you want to configure in the Project View.
This View allows to configure all preferences for your entire project, a folder, or a file.
You can change the severity of linting rules for your project.
You can modify conditional variables for VHDL 2019 projects.
You can configure include paths and initial defines for the SystemVerilog Preprocessor.
Make sure to click the APPLY button at the top right after making your changes.
Changes you make here will be stored in the .settings/ folder within your project.
This way, if you commit the settings with your project, they will be available for your fellow team members, also if they are using Sigasi Studio for Eclipse.
It is possible to run the User Interface of Visual Studio Code on one machine and do the actual development on another machine.
For example, you can be working on a Windows laptop at home, while the code lives on a Linux server in a datacenter at work.
On the laptop, you only need to install Visual Studio Code and the Remote SSH plugin.
The plugin connects with the remote server using SSH, and handles any setup required on the server.
The Sigasi extension only needs to be installed on the remote server.
Your code is kept on the server, there is no need to have a copy on the laptop. Documentation is available on the Visual Studio website.
Navigate to extensions (Ctrl+Shift+X or the icon on the left) and install the Remote - SSH extension.
From the Command Palette (Ctrl+Shift+P), select Remote-SSH: Connect Current Window to Host…. If you have an SSH config file, you can use an existing configuration here. Otherwise, select Add New SSH host and add the command to connect to your server. Note that you need to enter the full command line and not just the name of the server. Typically, the full command will look like ssh username@my.compa.ny .
To automate this, we recommend to use an SSH key-pair in combination with the SSH config file.
Once the connection is configured, connect to the server. In the bottom left corner of your VS Code window, you’ll find an indication of the remote connection.
In the connected VS Code window, navigate to plugins and install the Sigasi plugin on the remote server.
Navigate to the Explorer (e.g. Ctrl+Shift+E) and either open an existing workspace folder or clone a repository.
Check your Sigasi license setting. From the Command Palette (Ctrl+Shift+P), select Preferences: Open Settings (UI), and look for Sigasi: Path To License. With remote development, this is the license path on the server.
Note that the Sigasi VS Code extension with default settings will attempt to download a compatible Java runtime (JRE). If you want to use a JRE already installed on the server, look for Sigasi > Java: Path in the settings and enter he path to your java (11 or higher) executable. This is useful e.g. if the server doesn’t have internet access.
Now open a VHDL, Verilog or SystemVerilog file on the remote server.
Remote development license needs
When using the Sigasi extension in combination with the Remote SSH extension, the Sigasi license should be available on the remote host.
If you’re also using the sigasi extension locally, the license settings might be different for local and remote development. In that case, make sure to use the proper settings, depending on whether you’re developing locally or remote.
The settings from the User level will act as the default and can be overridden for each remote by setting the Remote [<remote name>].
The Sigasi extension supports semantic highlighting, however, some VS Code themes might not support it yet.
Be sure to use the default VS Code themes if you’re missing this feature.
In a theme that supports semantic highlighting, you’ll see that e.g. port, signal, and type names have a color that is different from the language keywords.
In a theme that does not support semantic highlighting, names like those of a port, signal, or type will have the default text color.
User-Defined Code Snippets
VS Code supports user-defined code snippets as explained here. To add snippets yourself, follow the steps below.
Open the Command Palette (Ctrl+Shift+P) and type Snippets
Select Snippets: Configure User Snippets
Type vhdl or systemverilog to open the corresponding JSON file where you can add your snippet like the examples below.
VHDL Snippet Example
{// Place your snippets for VHDL here.
"package declaration":{"prefix":"package","body":["package ${1:name} is","\t$0","end package $1;"],"description":"Insert package declaration"}}
SystemVerilog Snippet Example
{// Place your snippets for Verilog and SystemVerilog here.
"always posedge clk":{"prefix":"always","body":["always @(posedge ${1:clk}) begin","\t$0","end"],"description":"Insert an always block with posedge clock"}}
Sticky Scroll
You can use the sticky scroll to navigate through your HDL code more easily. This setting can be enabled with the key editor.stickyScroll.enabled
To check whether the Sigasi extension started successfully, you should navigate to Sigasi’s output view.
This can be done through the Command Palette (Ctrl+Shift+P) and select Sigasi: Open Log.
The Output View should say Language client connected from ...
The logs in the Sigasi output view contain possible errors from client and server.
If errors are present, you are advised to copy them and include them in your email to support+vscode@sigasi.com.
SLF4J Errors
The following error messages in the Output View can be safely ignored.
SLF4J: Failed to load class "org.slf4j.impl.StaticLoggerBinder".
SLF4J: Defaulting to no-operation (NOP) logger implementation
SLF4J: See http://www.slf4j.org/codes.html#StaticLoggerBinder for further details.
OutOfMemoryError: Java Heap Space
If Java runs out of memory, you will see a java.lang.OutOfMemoryError: Java heap space in the log.
To avoid this, go to the settings (Ctrl+Shift+P > Preferences: Open Settings (UI) > Sigasi).
Here you can set the Sigasi > Server: Arguments. Increase the value for Xmx to more than the default 3g.
On some occasions we might ask you to share the server logs.
Before obtaining the server logs it’s best to enable debug logging.
For more detailed logging, open the settings and change Sigasi > Server > Log: Level to debug.
The location of the server logs depends on your OS.
On Linux, the logs are below ~/.config/Code/logs
On Windows, the logs are in %AppData%\Code\logs
Then find [datetime]/window[1]/exthost/output_logging_[datetime]/[0-9]-Sigasi{Tracing}.log.
For each occurrence of [datetime], choose the most recent directory available.
We recommend to open the exthost folder using the command Developer: Open Extension Logs Folder.
Note: These logs contain file names from your project so only send them to us if you’re allowed to do so.
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This single page manual was generated on 2023-09-22.
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-icon in the status bar
at the bottom of the screen.
next the perspective icon. A window pops up in which you can select the perspective.
Create a new file
Create a new folder
Refresh the Project View
Toggle linking the Project View with the editor
Collapse all folders in the Project View
).
Expand the full hierarchy
Toggle showing only instantiations
Collapse the hierarchy
, the Project Explorer
will be linked to the Editor view. Now, the active file in the editor
view will always be selected in the Project Explorer.
and then
Customize view. You can then select a filter whose matching files
will be hidden in the view. For example, you can filter out all non-VHDL
or non-Verilog files.
in the top right corner of the project icon.
while files/folders with warnings are marked with a yellow triangle with black exclamation mark 
.
in the upper left corner.
.
.
Double-click in the Outline View to navigate to the corresponding
location in the editor.
.
to hide everything except instantiations and structural statements.
button if you first set up a Launch simulator.
button. Both SVG and PNG are supported. Choose a *.svg filename for SVG export or a *.png filename for PNG export.
button, you can toggle the display of comments on edge labels.
button, you can toggle the display of comments on edge labels. These labels show the code comments of the transition statements.
show dependencies of the entire project. Uncheck to focus on the dependencies of the active editor only.
Group design files per library
Show design units inside design files. The design units are prefixed with an abbreviation of their kind (architecture, module, package, …" >}}
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in the toolbar.
and the Show Previous Match arrow 
in the search result view. Note that all occurrences are highlighted and marked with a small arrow at the left border of the editor for easy recognition.
in the toolbar.
Horizontal Split shows 2 viewports on top of each other.
Vertical Split shows 2 viewports next to each other.
marks an info message that can be resolved automatically with a Quick Fix.
marks an info message.
marks a warning that can be resolved automatically with a Quick Fix.
marks an error that can be resolved automatically with a Quick Fix.
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icon.
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, on the right side of the status bar.
