In this screencast we demonstrate how to use VHDL 2019 projects in Sigasi Studio. It is an easy process, but you need to be careful that you use the correct Standard and IEEE libraries. We’ll start with creating a new project and next we’ll update an existing project to VHDL 2019.
First we will demo how to create a new VHDL 2019 project. This is easy, first enter a name for your project and next select 2019 as the version from the dropdown menu. Let’s create a new VHDL file to check everything is working as expected. When we open the properties view of this new file, we indeed see the correct version. Let us try a new VHDL 2019 syntax feature. Trailing semicolons in ports are now allowed. Indeed, we see no error. This was a most welcome language improvement!
Now let’s look at an existing project.
We decided we don’t want to type the end
component keyword in the file, so we have to update to VHDL 2019.
How do we do that?
You can right click on the file, folder or project to select the language version you want in the properties page.
But this is not enough. When you have any VHDL 2019 files in your project, you also need to update the VHDL2019 Standard and IEEE libraries. To update the libraries, you can right click on the common libraries folder and select “Reset common libraries”. Notice how other libraries remain untouched.
The changes to the file system are minimal. When we compare the latest version with the version in version control, we see changes in the .settings folder for the version settings file, and in the project file we see updated references to the new libraries.
That is how easy it is.
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