All Verilog and SystemVerilog projects use modules and module instantiations. In this video, we’ll show you how Sigasi Studio helps you get these instantiations right, even when the code changes.
See also
- Case statements in VHDL and (System)Verilog (blog post)
- Actual? Formal? What do they mean? (blog post)
- Wildcards in sensitivity lists in VHDL and Verilog (blog post)
- Recovering Verilog and SystemVerilog Parser (blog post)
- Prefix all signals in an instantiation (blog post)