Matching brackets are important when writing Verilog, VHDL and SystemVerilog. This video demonstrates how Sigasi Studio helps you to balance your brackets by automatically closing them. We will also show you a trick to quickly navigate to a matching bracket.
See also
- The benefits of early detection (screencast)
- Editing Broken Code in Sigasi Studio (screencast)
- Checking case statements in SystemVerilog (screencast)
- Multi-dimensional array and record checks in VHDL (screencast)
- Snake Case subword navigation and selection (screencast)