Sigasi Studio 4.9 brings another set of improvements. Our speed, memory and caching performance got better, and we have implemented new VHDL and (System)Verilog improvements. And one more thing … a lot of new (System)Verilog linting checks.
Read on for more details and other improvements.
We improved autocomplete for function and procedure arguments. When autocompleting a function or procedure Sigasi Studio now presents the complete list of arguments.
The quickfix for Add Declaration, Add All Declarations was improved. When the quickfix is applied, the editor scrolls to the new declaration and the data type is selected.
If this quickfix is triggered from the Problems View, multiple fixes can be selected. A subsequent undo, will undo all changes in a single step.
When you type a
use clause for a
package, but you did not declare the
library yet: Sigasi Studio now offers a quickfix to add the
library declaration automatically.
The biggest improvement in this release is the addition of many new (System)Verilog linting checks. This will surely help you save time on typical coding mistakes, especially if you have to follow strict coding guidelines and naming conventions.
In addition to the new linting checks Sigasi Studio 4.9 has following (System)Verilog improvements:
- Multiple SystemVerilog parser improvements and refinements
`includepaths with angle brackets (
- Properly display UDP items in hovers
`default_nettypedirective in unspecified
nettype of ANSI ports
- Better support for SystemVerilog
(System)Verilog linting checks
Sigasi Studio 4.9 introduces a long list of new linting checks for Verilog and SystemVerilog.
A syntax error is reported for:
- a mix of named and positional port connections or parameter overrides
- an empty parameter port list
- default values on ports where defaults are not allowed
- instance ports that are connected more than once
- too many instance port connections when ordered connections are used
- packed structs and unions without the
- multiple default members in an assignment
- incorrect use of semicolon
- empty assignments of ordered parameters
Case statement checks
A warning or error is reported for a case statement
- that does not cover all cases (likely mistake)
- with multiple
defaultclauses (only one is allowed)
- where the
defaultclause is not the last item (recommended)
- without a
defaultclause (recommended to have one)
Array and union assignment checks
Sigasi Studio checks for the following mistakes and recommendations:
defaultmember of an assignment pattern must be the last item
- A type key in assignment pattern is being overwritten
- Mixed named and ordered notation was used in an assignment pattern
- A member key is present more than once in a structure assignment pattern
Port and parameter checks
An error or warning is flagged if
- a parameter or port is not found within the instantiated unit
- a parameter or port, which does not have a default value, is missing in an instantiation
Sigasi Studio reports code where
- event control is not present at the top of an
alwaysconstruct (not synthesizable)
- non-blocking assignments are used in functions (semantic error)
- a register is initialized where it is declared (the initialization may not be synthesizable)
Code style checks
Sigasi Studio checks for a number of recommendations and guidelines that make (System)Verilog easier to understand and maintain. A warning or info marker is placed if the code does not comply with these rules. Note that some of these rules are set to ignore by default to avoid an excessive number of warnings in legacy code. If you want to enable these rules you can do so in Window > Preferences > Sigasi > (System)Verilog > Errors/Warnings. Sigasi Studio optionally checks for these rules:
- The file name matches the design unit (e.g. module)
- A file contains only one design unit
- Code lines are kept short (default 120 characters, so each line fits on the screen: easier to read)
- Spaces are used for indentation (so the code looks the same regardless of tab settings)
- In each file, a header comment is present and matches a certain pattern (e.g. with the company name and copyright statement)
- Named port connections are used for all instances with many ports (default for 3+ ports)
- Named parameter overrides are used for all instantiations with many parameters (default for 3+ parameters)
- Unit and port identifiers don’t contain successive or trailing underscores
- A function prototype has an explicit return type
- Function and task ports have an explicit direction
- Parameters have a default value
Other New and Noteworthy Changes
- Sigasi Studio can now run on Java 11
- The included Java Runtime Environment (JRE) in the stand alone version of Sigasi Studio was updated to Java 11. Note that the JRE is not updated with the update mechanism. If you want want to update the JRE, we recommend a new download.
- Improved layouting in graphical views
- We updated Eclipse in the standalone version to Eclipse 2020-06
- Updated the Xtext dependency to 2.22.0
- Better editor message when a browser view can not be loaded
- Removed the Sigasi Solarized themes
- Improved logging of system variables to help troubleshoot issues caused by third-party tool setup scripts.
- Improved the priorities of quick fixes. The Suppress quickfix is now presented as the last option.
- Tweaked subword selection for the
snake_casenaming convention. This makes editing identifiers easier in Sigasi Studio. We have made a screencast to demonstrate this.
- The Sigasi Studio Talkback server address was changed from
https://talkback-sigasi.sigasi.com. The option to enable unencrypted talkback was dropped.
- Sigasi Studio hangs when projects properties are changed while it is analyzing the project
- [(System)Verilog] Preprocessor: fixed issue with multi line string concatenation
- [VHDL] Allow to set VHDL version number when properties dialog is opened from an editor
- [(System)Verilog] Avoid duplicate design units in documentation export for (System)Verilog projects
- Plugin installation in Eclipse 2020-06 C/C++
- Wrong indentation in component quickfix
- Open design unit does not jump to declaration
- [(System)Verilog] Unexpected autocomplete suggestions in preprocessor directives
- [(System)Verilog] Ansi port connection is linked to wrong declaration
- A lot of other issues we could fix thanks to your Talkback reports
Startup time on Windows
If you experience long start-up delays on Windows 10, excluding the installation folder from the Microsoft Defender Antivirus scan might improve the start-up time. This is not specific for Sigasi Studio but affects all Eclipse installations.
Instructions on excluding the installation folder are available in this Microsoft support article.
- Sigasi Studio Standalone is supported on:
- Windows: Windows 10 (64 bit) or newer
- macOS 10.15 Catilina
- Linux: RedHat Enterprise Linux RHEL 7.7 (64 bit) or newer
- More information on supported OSes can be found on the Eclipse website
- Sigasi Studio as Plugin in your own Eclipse installation:
- Eclipse 4.7.3a Oxygen up to Eclipse IDE 2020-06
- Java JRE 8, 11
We recommend at least 4GB of memory available for Sigasi Studio, and you need about 300MB of free disk space.
Thanks for all the bug reports and enabling Talkback.