Sigasi Studio 4.2 brings a lot of extra SystemVerilog and VHDL linting and code checks. The Sigasi team also made it easier to configure linting rules per project. On top of that, Sigasi Studio 4.2 now has type time support for suppressing specific warnings.
Read below for more new and noteworthy changes and bug fixes.
More linting and code checks
New (System)Verilog checks:
- Warn for usage of
- Warn when using compiler directives as macro names
- Check for
packedkeyword in packed structs and unions
- Check for mixed positional and named port connections in instantiations
regkeyword is not allowed directly after a
- Warn when using VHDL keywords as identifiers for (System)Verilog declarations
The severity of the (non-syntax) checks can be configured in Window > Preferences > Sigasi > (System)Verilog > Errors/warnings
New VHDL checks:
- Warn when (System)Verilog keywords are used as VHDL identifiers
- Flag VHDL 87 file declarations as error
- Warn on empty loops
In earlier versions of Sigasi Studio you could suppress (also known as waive) warnings via the MarkerManager plugin. In Sigasi Studio 4.2 we refined this feature and now give type time feedback on suppressed markers. (documentation)
Check this video for an introduction to suppressing warnings in Sigasi Studio.
Configure linting severity per project [VHDL]
Sigasi Studio 4.2 presents a new Property Page that makes it easier to configure linting settings per project (or per file or folder).
Right click a project, folder or file and select Properties > VHDL Errors/Warnings. The settings are stored in the
.settings folder in your project. (documentation)
Other New and Noteworthy Changes
- (System)Verilog build performance enhancements
- [VHDL2008] Support defaults in function generics
- [Mixed] Add link from (VHDL) component ports to (System)Verilog module ports
- Support for Chinese, Japanese and Korean characters in documentation export (PDF)
- Apply dark theme on new Console View
- [Verilog] Disabled
.vextension interpretation for
.svfiles are always processed as SystemVerilog.
- Block diagram export should not use dark theme when the dark theme is enabled
- Updated Sigasi Studio Standalone version to Eclipse 2018-09
- Update to Xtext dependency to 2.15
- [VHDL] Better hovers for signals: also show type declaration
- [VHDL] Better hovers for component instantiations
- Better VUnit integration (requires VUnit version 4.0)
specifyblocks had an unexpected formatting
- Removed empty entries in (System)Verilog outline
- Fixed invalid errors on SystemVerilog sequences
- Fixed error in rename refactoring
- Fixed error in in SystemVerilog template editor
- Fixed Sigasi Studio freeze when license server disconnects
- Fixed error with grouped ports in custom block diagram configurations
- Fixed VUnit and GHDL preferences resetting on restart
- Fixed problem with temporary files in documentation generation
- Fixed problem with empty markdown lists in documentation generation
- Updating Sigasi Studio should not reset update sites configuration
- Block diagram export should not highlight selected items
- Fixed incorrect dead code warning
- Correctly handle comments in sort associations quick fix
- Fixed incorrect hierarchy for vector constant value
- Do not check out a Sigasi license when starting Sigasi as Eclipse plugin on a new workspace
- Fixed warning for components when ports in the entity are declared on the same line but the components are on separate lines
How to update?
If you have Sigasi Studio 4 installed, you can update or Download the Latest Version of Sigasi for a fresh install.