The second installment of Sigasi® Visual HDL™ (SVH™) 2024 introduces over a dozen new SystemVerilog linting rules, an improved Tools and Libraries setup flow, and VHDL 2019 Mode Views.

Please note that we will start ramping down support for Eclipse during 2025 to focus exclusively on VS Code for your benefit. This new release has made transitioning from VS Code to Eclipse even easier. We brought numerous improvements to VS Code, like Smart Indentation, performance improvements to autocomplete, and a smoother experience when first using the VS Code extension. Please enjoy and do get in touch with either our Sales Team or Support Team if you need any help transitioning to VS Code.

TL;DR

We’ve added over a dozen new SystemVerilog linting rules. They catch version-specific problems, duplicate signals, inheritance loops, and encourage good coding practices.

SVH now includes a simplified user-flow to set up tools and standalone libraries, use them across multiple projects, and share them with the entire team through a Library Database. We now also support the UVVM library natively (similar to the UVM library).

SVH now supports one of the most useful VHDL 2019 features: Mode Views. Mode views allow you to express interfaces, which drastically improves the readability and maintainability of VHDL designs.

Last but not least, this release includes a wide range of over 40 bug fixes and improvements.

New SystemVerilog Linting Rules and Quick Fixes

SVH linting rules ensure high-quality designs, and with these new additions, your code will be even more reliable and optimized.

New Naming Conventions

We extended the set of constructs that can be checked with naming conventions to include parameter types, macros, typedefs, structs, unions, and FSM variables. Furthermore, you can now define naming conventions for functions and tasks separately.

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Deep Nesting of Conditional and Loop Statements

Deep nesting of conditional and loop statements can result in poor readability. The rule optionally also checks nested conditional and loop generate statements. You can configure the depth level according to your preference.

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Order of Named Declaration List Does Not Match

Using named connections for port, argument, or parameter lists is considered a best practice, as it improves readability and prevents mistakes. Additionally, maintaining the same order for named connections as in the original declaration further enhances clarity, making the code easier to understand. The Quick Fix associated with this rule makes this a piece of cake.

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Names Differing Only by Case

Even though SystemVerilog allows this, using names that only differ in capitalization is bad practice. Minor typos easily become big mistakes.

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Duplicate Signal in Sensitivity List

In most cases specifying the same signal multiple times in a sensitivity list is an oversight. The Quick Fix associated with this rule allows for easily removing the redundant signal.

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Include of Globally Available Declaration

It is redundant to include modules, interfaces, user-defined primitives, and programs. These top-level declarations are already accessible without an include directive.

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Encourage Usage of Behavior-Specific Always Constructs

The behavior-specific always_[comb|latch|ff] constructs introduced with SystemVerilog should be used in favor of the general purpose always. They describe the intent, provide semantics that improve readability, and can be checked for correctness by tools. A Quick Fix makes it easy to adopt this good practice.

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Check Locally Unused Ports, Parameters, and Arguments

Leaving ports, parameters, or arguments unused leads to poorly readable code or can even be a bug. Enabling this rule helps improve the maintainability and correctness of your design.

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Cyclic Class Inheritance

Sometimes, cycles are accidentally introduced in the inheritance tree of your classes. A new rule will prevent you from making these mistakes.

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Various Checks for Labels

Labeling and naming your statements, blocks, and other constructs can help make your design easier to understand. However, it is easy to make mistakes when naming things. We added four new rules to ensure your labels are valid. All of these rules have an associated Quick Fix to resolve errors easily.

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Quick Fix to Change Version

Sometimes, a file can be wrongly interpreted as a Verilog file when it is a SystemVerilog file. A new Quick Fix helps you fix configuration mistakes like these.

Improved Tools and Libraries Setup Flow

The Tools and Libraries settings page lets you add tools and libraries. SVH supports UVM, UVVM, and custom libraries as well as libraries that are available with Vivado or Quartus installations.

When added, libraries are extracted to a Library Database. You can then share this database among multiple Sigasi projects and distribute it among your team to ensure everyone uses the same library versions. Learn more

Once all libraries you need are in the Library Database, you can select libraries you want to use in your project on the Common Libraries project properties (Right-click the project in the Project Explorer and click Properties).

If there are multiple versions of tools or libraries available in the Library Database, you can select the version that a project should use on the Active Tools and Libraries project preference page.

Note this new feature required our internal format to be overhauled.
See our upgrade instructions.

VHDL 2019 Mode Views

Mode views are SVH’s most requested VHDL 2019 feature. They allow you to define the direction of a collection of ports, making not only the type but also the directions reusable. Their closest comparison is SystemVerilog modports. You can start using mode views by configuring your files to VHDL 2019, which is easily done through a Quick Fix. Learn more

Update project to VHDL 2019 using a Quick Fix

Now that the mode views are understood by SVH, we can put them to good use.

Using mode views across multiple components

Finally, we declare a dut that internally uses the view modes.

You will be pleased to learn that mode views work throughout SVH, from syntax, linting rules, formatting, and hovers to Net Search and Graphical Views.

We even added two new linting rules, ensuring mode views are correctly defined.

Missing Mode for Record Element in Mode View

All record members must be defined in the mode view

The VHDL language specification mandates that every member declared in the record must have their direction defined in the associated mode view.

The missing elements can be added through a Quick Fix.

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Illegal Mode View Element Mode

The VHDL language specification forbids linkage as a direction in mode views.

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Further New and Noteworthy

Added over 30 new SystemVerilog static templates
Added over 20 new VHDL static templates
Changed required license for Documentation View to Designer Edition
Expanded Unsorted associations linting rule to all constructs supporting associations
Disabled the Configure library xilinxcorelib Quick Fix as it is superseded by the Tools and Libraries feature
Added an option to choose where to generate documentation
Edit License File now adds the license in the default location: ~/.sigasi.lic instead of in the current workspace
Improved the reliability of Talkback
VHDL Cleaned up autocomplete labels
Verilog Improved labels for typedef enums, unions, and structs

Talkback

Added events when a license is requested or checked
Added the product type to every message

Bug Fixes

Fixed issues with the Talkback server becoming unavailable and incorrectly disabling the license
Fixed some typos
Fixed license detection when there are empty entries
Scheduled a build after changes to the Minimal License to Checkout
Fixed incorrect semantic highlighting in rare cases
Fixed the version number in generated documentation
VHDL Redirect to the original unisim_retarget_VCOMP.vhd instead of retarget_VCOMP.vhd when the protected unisim_retarget_VCOMP.vhdp is referenced
VHDL Fixed the Update VHDL version Quick Fix for external files
VHDL Fixed highlighting for Show in > Outline
VHDL Fixed hovers for VHDL 2019 conditional variables
VHDL Fixed missing FSM dead state detection
VHDL Fixed Set as Top Level when the matching entity is in a different file
VHDL Fixed missing hover for large physical literal values, e.g, 3333 min
VHDL Fixed false positive “No matching subprogram was found” error for protected type bodies
VHDL Removed Add Declaration Quick Fix from character literals
Verilog Consistently use Verilog/SystemVerilog to refer to Verilog and/or SystemVerilog
Verilog Fixed recognition of include files starting with a colon character
Verilog Fixed navigation through double-click for Verilog items in the Hierarchy View
Verilog Fixed false positive deprecated macro warnings in disabled preprocessor branches

Upgrade Instructions

The VHDL linting rule 94 was changed from ignored to info. If you see more info issues and you would like to revert to the old behavior, you can do so by configuring the severity of the Incomplete port map or generic map: using defaults linting rule to ignore in the Project Preference View.

The libraries extracted in SVH 2024.1 are not compatible with SVH 2024.2. To migrate, rerun the extraction in SVH 2024.2 and synchronize project configuration for libraries. If you have not yet used library extraction or have not used SVH 2024.1, no action is required. Learn more

Update or Install

You can download the stand-alone version of the latest preview.

You can also update automatically when setting Preferences > Install/Update > Available Software Sites > Add… : https://download.sigasi.com/sigasi-studio/preview/composite/

SHA sums (more info) can be checked via https://download.sigasi.com/sigasi-studio/preview/latest/eclipse-sha1.txt .

System Requirements

Sigasi Visual HDL in Eclipse requires:

Windows 10 or Windows 11 64-bit
RedHat Enterprise Linux RHEL 8 or 9 64-bit
- Sigasi Visual HDL depends on libXss.so, which is obtainable by installing libXScrnSaver
- Sigasi Visual HDL depends on webkit2gtk4.0, which is installable through your package manager of choice
- You can find more information on supported Linux Operating Systems on the Eclipse website

Sigasi Visual HDL as a plugin in your existing Eclipse installation requires:

Eclipse IDE 2021-03 up to and including Eclipse IDE 2024-09
Java JRE 11 or 17

We recommend having at least 8GB of memory and about 1GB of free disk space available for Sigasi Visual HDL.

Feedback

We welcome your feedback through the usual channels or the comments below. Note that we clear the comments on this page after each official release.