Sigasi 2.10 brings a new State Machine navigation feature, automatic hierarchy refresh, avoiding full rebuilds and more.
We introduce a new, power navigation feature for finite state machines (FSMs) in VHDL. If you press Ctrl and click on the name of a state. You jump directly to the relevant when part of your case statement. There is a screencast, Navigation, to show how it works.
The hierarchy view now automatically refreshes itself when you save your design files. You can turn the automatic refresh on and off by toggling the refresh button.
We have added extra intelligence to avoid full rebuilds. In two important cases, the older versions of Sigasi triggered unnecessary full rebuilds: (1) while the user is mapping VHDL Libraries or (2) if other EDA tools write and delete binary files in the project directory. The new version makes an extra effort to avoid full rebuilds, saving you time.
modelsim.inias parameter when it exits in the root folder of the project.
- Code folding for blocks (ticket 2332)).
- Avoid unnecessary clean builds when closing external files.
- If the
vcomcompiler takes too long, you can terminate the
vcomprocess by pressing the stop icon in the progress view.
- Better CSV export when a project depends on other projects (ticket 2284)).
- ticket 2323 : Fully qualified names in component instantiations
- ticket 2342 : Corrected scoping of end labels
- ticket 2321 : Errors in Custom VHDL Templates User Interface when using the Anywhere context.
- ticket 2326 : Display
spaces instead of
%20in the search view
- ticket 2335 : Error when triggering quick-fix if certain uses clauses are used.
- ticket 2343 : Better recovery for incorrectly edited
- ticket 2344 : Store the toggle state of the instantiations filter in the hierarchy view when Sigasi is restarted.