People hate VHDL. People love VHDL. But most of all people love to complain about VHDL. I want to make a list of reasons to love or hate VHDL. Not to complain about them and not to prove that VHDL is better or worse than Verilog. No, I want to make this list so that we can use the strengths of VHDL, and find ways to overcome its weaknesses.
For all the Verilog guys reading this: I know Verilog deserves the same analysis. Since we do not have a Verilog product available today, I will save this discussion for later. In the meanwhile, please give me a reason to put Verilog at the top of our priority list.
- VHDL allows me to write a hardware design at a high level of abstraction.
- VHDL is strongly typed so a large class of errors get flagged at compile time.
- VHDL allows me to create new datatypes, so that I can write concise code.
- VHDL has good mechanisms for code reuse, such as datatypes, functions, procedures and packages.
- The VHDL syntax is not consistent, and hard to remember.
- The VHDL syntax is very verbose: you have to type a lot of words to get something done.
- VHDL is pedantic in its requirements for type casting and conversions.
- VHDL does not define a file and directory structure; everybody uses their own file structure.
I have several more items for each list, but I am more interested in your reasons for loving and hating VHDL. Please let me know!