As a visitor of the Sigasi website, you are probably interested in Sigasi’s products. Therefore, there is a good chance that you are using VHDL and that you like it. (If you are here for other reasons or if you hate VHDL, you are most welcome too :-))
Call yourself lucky. If it had depended on some EDA heavyweights, you would not have had that choice today. You would have been forced to use Verilog.
In 1995, Joe Costello gave a keynote speech at the OVI conference. We only know indirectly and approximately what he said. I am quoting from John Cooley’s deepchip:
VHDL is one of the biggest mistakes the Electronics Design Automation industry has ever made. A $400 million mistake. Wouldn’t this money have been better spent on handling sub-micron design, testability issues, or even a new type of HDL that had significantly more capabilities than what Verilog and VHDL offer today?
- Joe Costello, then the CEO of Cadence, in his 1995 OVI keynote
There you have it: the CEO of the dominant EDA company at the time called your favorite HDL a mistake. In those years, Verilog and VHDL were the main HDL contenders, and Cadence dominated the Verilog simulation market. So what Mr. Costello really was saying is that a monopoly for Verilog (and his company) would be in the broader interest of the industry. I don’t remember anymore, but it’s easy to imagine how the Verilog and VHDL camp must have reacted. More significantly however, I don’t recall that anyone warned about the economic consequences of such a scenario: the fact that a monopoly is generally a really bad idea.
It is normal for a company to strive for a monopoly as the ultimate form of success. However, it is equally clear that a monopoly is not in the general interest of an industry and its customers. With a monopoly, there is no competition. When competition goes away, so does innovation. I’m quite sure Mr. Costello would agree. So why then did he advocate such a scenario?
Perhaps he was not able to detach from the short-term interests of his company and himself. I would find that quite disappointing, but I may be naive.
Another possibility is that Mr. Costello didn’t see any need for further innovations in the HDL language space. He hints at “a new type of HDL” as if it would be straightforward to find an industry consensus on how it should look like. That was not very realistic. In practice, many HDLs and HVLs have been proposed and developed after 1995, and they typically go into different directions. This “waste of efforts” is typical for competitive markets. I don’t think there is a viable alternative to find out what the market really wants.
A final possibility, perhaps the most likely one, is that Mr. Costello was questioning the added value of VHDL itself. Perhaps he held the opinion that there was nothing in VHDL that Verilog could not do equally well or better. On this point I disagree strongly. That will be the topic of my next post.
In the mean time I wish you all a lot of fun with your favorite mistake.
This article is part of Jan’s blog about his personal views on HDL design.
- Time for reflection (opinion)
- VHDL's crown jewel (opinion)
- Verilog's major flaw (opinion)
- EDA 2.0 (opinion)
- The most needed EDA innovation (opinion)