Synthesis was my first love

Posted on 2009-12-03 by Jan Decaluwe
Tagged as: JanHDL

In my previous blog post, A 20-year old relationship, I mentioned that when I first met VHDL, it wasn’t love at first sight. However, I did experience love at first sight with another hardware design technology: synthesis.

It was early 1990, and I had just started as a hardware designer at Alcatel. My very first assignment was an evaluation of a new tool called Synopsys Design Compiler. Within a few days after I got my hands on it, I was hooked. This was a tool that could convert a non-trivial hardware description “program” into an efficient implementation. I felt that I had discovered the missing link in the vision that hardware design is a kind of software development.

I remember that I tried out one Verilog example after another on the tool. Each time I thought: “it won’t be able to handle this one”. Yet each time the tool surprized me as it came back with a correct, efficient implementation. And on every occasion, my conviction grew that this was “it”. I just “knew” that this tool was going to revolutionize the industry. I have been wrong with many predictions, but with this one I have been absolutely right.

Experimenting with Synopsys Design Compiler was a great experience, a time full of excitement and new insights. Only a few other technologies have made a similar first expression on me. Among them are the Netscape browser and the Python programming language, but Synopsys DC is still my number one. Such an experience does not happen every day, but it may have profound implications. It may change your life.

Synopsys Design Compiler did change my life. Without it, I wouldn’t have bothered learning Verilog or VHDL, and I probably would have left the hardware design field a long time ago. Most importantly, I might never have started a company.

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