Code refactoring: Emacs VHDL mode vs Sigasi

Posted on 2011-06-22 by Philippe Faes
Tagged as: EmacsVHDL

Last week, I talked about that there is No VHDL Rename in Emacs VHDL mode. Rename is just the tip of the iceberg when it comes to code modifications or refactorings (What is hardware refactoring?). There are dozens of well documented and automated code refactorings… in the world of software engineering. In hardware land, however, only a few refactoring tools exist. (You’re lucky: Sigasi is one of them!) And all the hardware refactoring tools put together still look pale compared to Eclipse JDT, the weapon of choice for many Java refactorers.

Cutting to the chase: nobody is going to build a decent automated refactoring tool, based on regular expressions. Or on LISP, or on Emacs. That’s just not the right tool for the job. If you stick with a development environment that comes with a built-in VHDL parser, you’re betting on the right horse. This technology is ready for some extra innovative fireworks.

At Sigasi, we have some refactorings implemented and shipped to our customers: rename, add port, encapsulate statements.

Doing any of these refactorings by hand can easily take half an hour to several hours. With the right tool (and Emacs VHDL is not it!) in your hands, it will only take a minute.

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