Setting Up a UVM Project

Sigasi Visual HDL (SVH) provides several features that help write UVM testbenches. However, you first have to set up a project with a UVM library to use these features.

This page describes how to set up a UVM project in SVH. The instructions described here are general; refer to the Project Setup section for details on project setup.

  1. Open the folder of your UVM project and add Sigasi support to the project. The project will have a lot of errors at this point, indicating missing declarations and undefined macros.

  2. Add the UVM sources to the project by adding a linked folder to the source folder of the reference implementation of UVM. At this point, most of the errors should be gone. If you don’t have UVM source files on your system yet, you can download them here .
    Note: we highly recommend adding this linked folder to the Common Libraries folder, since sources in this folder are treated as read-only and are not checked for errors. We also recommend that every file except uvm.sv be excluded from being built.

  3. Finally, update the include paths, which you can easily do through a Quick Fix. There should be a number of Preprocessor include paths are not configured correctly warnings on include statements of UVM header files. You can easily find these warnings through the Problems View. A Quick Fix that automatically updates the include paths of a project is available on these warnings. A bulk mode is also available, allowing you to fix all the missing include paths in the current project. Alternatively, the include paths can be changed through the Add to Include Paths context menu item, which is available in the Sigasi Projects View. You can also manually update the include paths through the Preference View, under the Verilog Preprocessor page.

After completing the steps above, all of the problems related to UVM configuration should be gone. You can now use all the UVM features, such as the UVM Diagram and the UVM Topology View.