Templates Editor

The templates editor allows you to define reusable code blocks encompassing frequently used elements like process blocks, signal declarations, or loop constructs. You can seamlessly insert these templates into your VHDL or Verilog code at the cursor position. This eliminates the need for manual typing of repetitive structures, saving you valuable time and reducing the potential for inconsistencies.

You can access the editor through the preferences (search for sigasi.userDefinedTemplates). The preference you’ll find has a button to edit your custom templates. It is also available through Ctrl + Shift + P > Sigasi: Open Templates Editor.