Sigasi Visual HDL (SVH) offers Smart Indentation for both VHDL and Verilog. When enabled, the indentation level is automatically adjusted based on the context and the code being written.
Configuration
To make use of SVH’s Smart Indentation, make sure the Editor: Auto Indent setting is set to full. To further configure the inserted indentation, the following settings can be used:
- Editor: Insert Spaces: To insert spaces rather than tabs.
- Editor: Indent Size: To configure the size of the indentation.
- Editor: Detect Indentation: To dynamically adjust the previous two settings based on the indentation style used in the current file.