Project Formatting Configuration

You can configure VHDL formatting preferences for a project in Sigasi Visual HDL (SVH) to ensure consistent formatting across platforms and among users working on the same project.

Properties

• Enable project formatting settings, dictates whether or not the formatting preferences specific to this project are enabled
• Preserve newlines, the formatter respects newlines: it does not add or remove any
• Use vertical alignment, align lists such as generics or ports
• Lowercase/Uppercase keywords, controls how the formatter transforms keywords: lowercase, UPPERCASE, or ignore
• Alignment column for trailing comments, the column in the line to which the trailing comments will be aligned