Sigasi Visual HDL (SVH) has a number of checks on VHDL coding style.
Extended identifier contains whitespace
SVH flags an info message when using extended identifiers that contain whitespace. Particularly in mixed-language designs, these identifiers may cause problems in Verilog and SystemVerilog as they use whitespace to mark the end of an extended identifier.
signal \foo bar\ : std_logic -- identifier with spaces: not recommended!
Line is too Long
For legibility, it is recommended to keep lines of code short. SVH warns if a code line is longer than a certain length. The maximum length is set to 120 characters by default, but this can be configured on the Errors/warnings page of the project settings or workspace preferences.
Magic number, bitstring, or string in statement
A design often requires certain constant numbers, bitstrings, or string literals. To optimize code maintainability, it is recommended to use generics or define such literals in constants rather than hardcoding them directly into statements. If this rule is enabled, SVH will flag all magic numbers, bitstrings, and strings used in statements.
The rule can be configured to work on numbers, bitstrings, and/or strings. It is also possible to configure a set of literal values that are allowed in statements, this is done using a regular expression .
...
s_output <= func(s_input, 4032);
...
...
constant Size : integer := 4032;
...
s_output <= func(s_input, Size);
...
Sequence of operators without parentheses
When writing an expression containing a sequence of operators the order of execution might not always be obvious. For this reason, it is recommended to add sufficient parentheses to expressions that include multiple non-associative operators. If this rule is enabled, SVH will flag all such expressions.
s_output <= s_input mod 4 + 3;
s_output <= (s_input mod 4) + 3;
Constant width vector assigned to signal
To optimize code maintainability and portability, it is not recommended to assign vectors of constant width to signals. If this rule is enabled, SVH will flag all signal assignments that use constant width vector literals.
s_output <= "00000000";
s_output <= (others => '0');
Rule configuration
These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured with the following template:
# Extended identifier contains whitespace
228/severity/${path}={error|warning|info|ignore}
# Line is too long
97/severity/${path}={error|warning|info|ignore}
97/params/max_line_length/${path}=${integer} # at least 1
# Magic number, bitstring, or string
235/severity/${path}={error|warning|info|ignore}
235/params/check_number/${path}={true|false}
235/params/check_bitstring/${path}={true|false}
235/params/check_string/${path}={true|false}
235/params/allow_literal_pattern/${path}=${regex}
# Sequence of operators without parentheses
230/severity/${path}={error|warning|info|ignore}
# Constant width vector assigned to signal
231/severity/${path}={error|warning|info|ignore}