When a vector signal is used as a conditional expression or as an argument to logical operators (e.g.
!) it’s implicitly converted to scalar value
0 (false) if all vector bits are zero or to
1 (true) otherwise. It’s not clear in this case if such conversion was intentional or by mistake, and a scalar type or bitwise operator, such as
~ was expected.
module ff(input clk, [7:0] d, rst, output [7:0] q); always_ff @(posedge clk) begin if (rst) // Implicit conversion of 'logic [7:0]' to boolean q <= 0; else q <= !d; // Implicit conversion of 'logic [7:0]' to boolean end endmodule
It may be better to explicitly compare the vector with zero (
vec == 0 or
vec != 0) if that’s your intent.
Note that this rule is disabled (set to
IGNORE) by default.
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template: