Verilog Unused Declaration

A declaration that is never used does not contribute anything to a design and can be an indication of a coding error. Unused declarations will be marked as warnings.

module code;
    logic var1 = 0;
    logic var2 = 1;

    initial $display(var2);

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template: