Different EDA tools have extended the Verilog and SystemVerilog standard in diverging ways. To maximize tool compatibility, Sigasi allows some constructs not included in the standards. The linting rules listed below mark the usage of such constructs as a warning, which can be disabled individually if you use a tool that allows a particular construct.
Whitespace following a backtick
Some tools allow additional whitespace following the backtick of a preprocessor directive.
`define A 1
` define B 2 /* unexpected whitespace following the backtick */
Invalid preprocessor syntax
Some directives and escape sequences such as `` and
`" can only be used inside the body of a macro definition.
Some tools are however more lenient, allowing them also elsewhere.
var asdf = `"asdf"; // Unexpected `" directive outside macro body
Rule configuration
These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured with the following template:
117/severity/${path}={error|warning|info|ignore} # Whitespace following a backtick
121/severity/${path}={error|warning|info|ignore} # Invalid preprocessor syntax