Verilog coding style

Sigasi Studio has a number of checks on Verilog coding style.

File name does not match design unit

It is recommended that the base name of the filename is the same as the name of the design unit (e.g. module) in the file (rule 17). Sigasi Studio flags a warning if that is not the case.

E.g. module my_module should be in a file my_module.v or my_module.sv .

In a file with multiple design units (which is not recommended), this rule is not active.

File contains multiple design unit

It is recommended that a (System)Verilog file contains only one design unit (rule 18). Sigasi Studio flags a warning if that is not the case.

Verilog code line too long

For legibility, it is recommended to keep lines of code short (rule 20). Sigasi Studio flags a warning if a code line is longer than a certain length. The maximum length is set to 120 characters by default, but this can be changed in the project linting settings (${project_location}/.settings/com.sigasi.hdt.verilog.linting.prefs). E.g.:

20/params/max_line_length/<project>=123

Tabs are not allowed

While this may potentially be controversial, TABs are forbidden in majority of coding standards in the HDL domain with the motivation of code not looking the same regardless of the editor/settings used. This check is off by default but it can be enabled in the workspace or project linting settings (rule 21).

File header comment does not match required pattern

Many conding standards require presense of header comment in every file, matching a certain format. Sigasi Studio can check whether the file header comment matches a pattern (rule 22). By default, the pattern is empty which turns this check off. The pattern can be configured through *Window > Preferences > Sigasi > (System)Verilog > Naming conventions > File header and uses the Java regex syntax.

Multiple statements per line

For readability, each statement should be on a separate line. Sigasi Studio will flag a warning if a line of code contains multiple statements (rule 47).

module rule47;
    reg A, B, C, D, K, M;
    reg EN;

    assign A = B & C, D = K & M;    // multiple statements in one line: less readable

    assign A = B & C;               // one statement per line: more readable
    assign D = K & M;

    always@(*)
        if(EN==1'b1) begin
            A = B & C; D = K & M;   // multiple statements in one line: less readable

            A = B & C;              // one statement per line: more readable
            D = K & M;
        end
		
endmodule

Trailing comma is not recommended

Sigasi Studio will flag a warning if a parameter list has a trailing comma (rule 52). Most EDA tools will treat a trailing comma as a syntax error.

module ugly #(WIDTH = 16 , ) (
    // ...

module nice #(WIDTH = 16) (
    // ...

Project specific setting of these rules

These rules can be disabled for your project, or its severity can be modified in the project linting settings.

Manual configuration in ${project location}/.settings/com.sigasi.hdt.verilog.linting.prefs:

17/severity/<project>=IGNORE

18/severity/<project>=IGNORE

20/severity/<project>=IGNORE

21/severity/<project>=IGNORE

22/severity/<project>=IGNORE

47/severity/<project>=IGNORE

52/severity/<project>=IGNORE