Verilog Coding Style

Sigasi Studio has a number of checks on Verilog and SystemVerilog coding style.

Empty loops and conditional branches

While occasionally intended, this construction is confusing, and often the result of a typo. Sigasi will flag a warning if an empty block is found (rule 1). In RTL code for synthesis, empty conditional branches in sequential code can cause unwanted latch generation. There may be a couple of reasons why an empty block is present in your code:

  • It is an unintentional omission and should be fixed to prevent unexpected behavior.
  • Some functionality is not yet, or never will be, supported. In this case, a $fatal (or similar) system task should be called.
  • It is intentionally blank. In this case, a comment should clarify the reason why.

File name does not match design unit

It is recommended that the base name of the filename is the same as the name of the design unit (e.g. module) in the file (rule 17). Sigasi Studio warns if that is not the case.

For example, module my_module should be in a file named my_module.v or my_module.sv .

In a file with multiple design units (which is not recommended), this rule is not active.

File contains multiple design unit

It is recommended that a Verilog file contains only one design unit (rule 18). Sigasi Studio warns if that is not the case.

module foo;
endmodule

module bar;
endmodule

Verilog code line too long

For legibility, it is recommended to keep lines of code short (rule 20). Sigasi Studio warns if a code line is longer than a certain length. The maximum length is set to 120 characters by default, but this can be changed in the project linting settings.

Tabs are not allowed

While this may potentially be controversial, TABs are forbidden in the majority of coding standards in the HDL domain with the motivation of code not looking the same regardless of the editor/settings used. This check is set to ignore ignore by default but it can be enabled in the workspace or project linting settings (rule 21).

File header comment does not match required pattern

Many coding standards require the presence of a header comment in every file, matching a certain format. Sigasi Studio can check whether the file header comment matches a pattern (rule 22). By default, the pattern is empty which disables this check. The pattern can be configured through Window > Preferences > Sigasi > (System)Verilog > Naming conventions > File header and uses the regex syntax. More information on file header comment checking is available here.

Report encrypted regions

Starting with Verilog 2005, regions of Verilog and SystemVerilog files may be encrypted to protect intellectual property. Sigasi obviously won’t check the content of these regions. Optionally, Sigasi can flag the presence of encrypted regions in your code (rule 44). This rule is off by default (i.e. set to IGNORE) but can be enabled (as info, warning, or error) as required.

Multiple statements per line

For readability, each statement should be on a separate line. Sigasi Studio will flag a warning if a line of code contains multiple statements (rule 47).

module rule47;
    reg A, B, C, D, K, M;
    reg EN;

    assign A = B & C, D = K & M;    // multiple statements in one line: less readable

    assign A = B & C;               // one statement per line: more readable
    assign D = K & M;

    always@(*)
        if(EN==1'b1) begin
            A = B & C; D = K & M;   // multiple statements in one line: less readable

            A = B & C;              // one statement per line: more readable
            D = K & M;
        end
endmodule

Regular expressions compatibility

Naming conventions in Sigasi use RE2/J regular expressions. RE2/J expressions mitigate potential performance problems that are caused by some shapes of regular expressions using the regular Java regular expression engine. Sigasi will warn if a naming convention rule contains a regular expression that is incompatible with RE2/J (rule 58).

Rule configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured with the following template:

1/severity/${path}={error|warning|info|ignore} # Empty loops and conditional branches
17/severity/${path}={error|warning|info|ignore} # File name does not match design unit
18/severity/${path}={error|warning|info|ignore} # File contains multiple design unit

# Verilog code line too long
20/severity/${path}={error|warning|info|ignore}
20/param/max_line_length/${path}=${integer} # at least 1

21/severity/${path}={error|warning|info|ignore} # Tabs are not allowed
22/severity/${path}={error|warning|info|ignore} # File header comment does not match required pattern
44/severity/${path}={error|warning|info|ignore} # Report encrypted regions
52/severity/${path}={error|warning|info|ignore} # Multiple statements per line
58/severity/${path}={error|warning|info|ignore} # Regular expressions compatibility