Verilog reg and logic Datatype

In SystemVerilog, the reg datatype is deprecated. It is recommended to use the logic datatype instead.

Sigasi Studio warns when the reg datatype is used in SystemVerilog.

A Quick fix is available to convert reg into logic.

module my_module;
    reg   deprecated;
    logic good;
endmodule

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:

3/severity/${path}={error|warning|info|ignore}