Verilog reg and logic datatype


In SystemVerilog, the reg datatype is deprecated. It is recommended to use the logic datatype instead.

Sigasi Studio flags a warning when the reg datatype is used in SystemVerilog.

A Quick fix is available to convert reg into logic.

module my_module;
    reg   deprecated;
    logic good;
endmodule

Project specific setting of this rule

This rule can be disabled for your project, or its severity can be modified in the project linting settings.

Manual configuration in ${project location}/.settings/com.sigasi.hdt.verilog.linting.prefs:

3/severity/<project>=IGNORE