Verilog processes


(System)Verilog always constructs without an event control statement at the top cannot be synthesized. Additionally, they would activate in random order at the moment 0 at beginning of a simulation.

Sigasi Studio flags a warning for always blocks without event control statement at the start.

A good way to correct this description is to place the timing control statement at the top.

module test(clk, data_in, data_out);
    input clk;
    input[3:0] data_in;
    output reg[3:0] data_out;
    
    always
    begin
        data_out <= data_in;
        @(posedge clk); // Timing control not at the top of 'always'
    end
endmodule

module test(clk, data_in, data_out);
    input clk;
    input[3:0] data_in;
    output reg[3:0] data_out;
    
    always @(posedge clk)
       data_out <= data_in;
    
endmodule

Project specific setting of this rule

This rule can be disabled for your project, or its severity can be modified in the project linting settings.

Manual configuration in ${project location}/.settings/com.sigasi.hdt.verilog.linting.prefs:

27/severity/<project>=IGNORE