SystemVerilog has three specific always procedures: always_comb, always_latch and always_ff. These should be used in favor of general purpose always in synthesizable designs because:
- they describe the intent of the always procedure
- they provide semantics that improve readability
- tools can additionally check for correctness concerning their behavior
Sigasi Visual HDL (SVH) reports generic always procedures as a warning.
module m (input clk);
always @(clk) begin
end
endmodule
SVH offers Quick Fixes to use a specific always procedure instead.
Rule configuration
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:
170/severity/${path}={error|warning|info|ignore}