Verilog parameters


Sigasi Studio flags a warning if a parameter is declared without a default value. Syntactically this is allowed, since the instantiating modules should provide the value to the instance parameter. However, it is undesirable since it makes the definition dependent on particular hierarchy and limits code reusability. In addition, it is creating elaboration errors when attempting to use such module as a top-level.

module badcode;
	parameter P;
	initial
	    $display(P);
endmodule

module goodcode;
	parameter P = 0;
	initial
	    $display(P);
endmodule

Project specific setting of this rule

This rule can be disabled for your project, or its severity can be modified in the project linting settings.

Manual configuration in ${project location}/.settings/com.sigasi.hdt.verilog.linting.prefs:

19/severity/<project>=IGNORE