Sigasi Studio validates the use of parameters in (System)Verilog.
Parameters without a default value
Sigasi Studio flags a warning if a parameter is declared without a default value (rule 19). Syntactically this is allowed, since the instantiating modules should provide the value to the instance parameter. However, it is undesirable since it makes the definition dependent on particular hierarchy and limits code reusability. In addition, it is creating elaboration errors when attempting to use such module as a top-level.
module badcode; parameter P; initial $display(P); endmodule module goodcode; parameter P = 0; initial $display(P); endmodule
Parameters wider than 32 bits
Sigasi Studio flags an error if a parameter is declared with a default value which is wider than 32 bits (rule 48). If a parameter needs to be wider than 32 bits, its width must be specified.
parameter p = 'h764321098; // default value is 36 bits wide, width must be specified parameter [35:0] q = 'h764321098;
Empty parameter not allowed
The Verilog standard doesn’t allow empty parameters.
module dut # (parameter WIDTH = 42, ) (input clk); endmodule; // dangling comma is not allowed module dut # (parameter WIDTH = 42 ) (input clk); endmodule;
Empty parameter overrides not allowed
The Verilog standard doesn’t allow empty parameter overrides.
module test; sub#(8, 16, ) inst(); // dangling comma is not allowed endmodule module test; sub#(8, 16 ) inst(); endmodule
Project specific setting of these rules
These rules can be disabled for your project, or its severity can be modified in the project linting settings.
Manual configuration in ${project location}/.settings/com.sigasi.hdt.verilog.linting.prefs
:
19/severity/<project>=IGNORE
48/severity/<project>=IGNORE
53/severity/<project>=IGNORE
54/severity/<project>=IGNORE