In Verilog, it is discouraged to include files that have globally scoped top-level declarations (e.g. modules, user-defined primitives).
Given the files f1.sv and f2.sv, whose content is, respectively, as follows:
module f1(); endmodule : f1
class f2; endclass : f2
Includes of f1.sv would be marked.
`include "f1.sv"
`include "f2.sv"
Transitive includes are not highlighted. If there is a file f3.sv that includes f1.sv, the include of f1.sv in f3.sv would be highlighted, but includes of f3.sv would show no warnings.
By default, included files that contain top-level packages are not reported. However, it’s possible to configure the rule to report such include statements.
Rule configuration
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:
168/severity/${path}={error|warning|info|ignore}
168/params/report_packages_in_include_files/${path}={true|false}