The use of VHDL keywords as a (System)Verilog module name is not recommended. In mixed-language projects in particular it could lead to unexpected results. Sigasi Studio flags a warning when a VHDL keyword is used as a module name (rule 7) .
module entity; endmodule module my_module; endmodule
The following naming cases should be avoided in Verilog identifiers:
- module or port name ending with underscore:
- any name having consecutive underscores:
The recommendation is mainly based on tool and library compatibility issues. This is a typical unofficial convention to reserve those types of names as internal to tools.
Sigasi Studio flags a warning for consecutive underscores (rule 42) and trailing underscores (rule 43) in module and port names.
module bad__code(input clk_); endmodule module goodcode(input clk); endmodule
These rules can be disabled for your project, or its severity can be modified in the project linting settings.
Manual configuration in