VHDL keywords as module name
The use of VHDL keywords as a (System)Verilog module name is not recommended. In mixed-language projects in particular it could lead to unexpected results. Sigasi Studio warns when a VHDL keyword is used as a module name (rule 7).
module entity; endmodule module my_module; endmodule
Underscores in identifier names
The following naming cases should be avoided in Verilog identifiers:
- module or port name ending with an underscore:
bad_ - any name having consecutive underscores:
very__bad
The recommendation is mainly based on tool and library compatibility issues. This is a typical unofficial convention to reserve those types of names as internal to tools.
Sigasi Studio warns for consecutive underscores (rule 42) and trailing underscores (rule 43) in module and port names.
module bad__code(input clk_); endmodule module goodcode(input clk); endmodule
Non-packed member in packed struct or union
Packed structures and unions can only contain members of packed data types and integer data types (rule 59).
class AClass; endclass
typedef struct packed { int a; } intstruct;
typedef struct packed { real a; } realstruct;
typedef struct packed { AClass a; } classstruct;Illegal type in untagged union
Dynamic types and chandle types can not be used in untagged unions (rule 60).
class AClass; endclass
typedef union { int a; } intunion;
typedef union { string a; } stringunion;
typedef union { AClass a; } classunion;Rule configuration
These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured with the following template:
7/severity/${path}={error|warning|info|ignore} # VHDL keywords as module name
42/severity/${path}={error|warning|info|ignore} # Consecutive underscores
43/severity/${path}={error|warning|info|ignore} # Trailing underscores