Verilog assignment patterns


Sigasi Studio has several checks on Verilog assignment patterns.

Default member must be last

Concrete assignments must preceed more general assignments, otherwise some of those assignments might be ignored (rule 28). In particular:

  • for arrays, default must be at the end of the list
  • for structures, default must be at the end, but type-default must be after the particular member assignments
module badcode;
    int a[3:0] = '{0: 5, default: 0, 3: 1};
   
    typedef struct {
        int x;
        int y;
        real radius;
    } circle_t;
   
    circle_t b = '{default: 0, x:1};
   
    circle_t c = '{default: 0, real: 0.0};
   
endmodule

module goodcode;
   
    int a[3:0] = '{0: 5, 3: 1, default: 0};
   
    typedef struct {
        int x;
        int y;
        real radius;
    } circle_t;
   
    circle_t b = '{x:1, default: 0};
   
    circle_t c = '{real: 0.0, default: 0};
endmodule

Only one default member expression is allowed

Sigasi Studio flags an error when expressions have multiple default assignments (rule 29). In particular:

  • arrays cannot have multiple default assignments
  • structures cannot have multiple default assignments or multple type-default assignments
module badcode;
    int a[3:0] = '{default: 1, 0: 2, default: 3};        // multiple default assignments
    
    typedef struct {
        int x;
        int y;
        real radius;
    } circle_t;
    
    circle_t b = '{default: 0, radius: 1.0, default: 0}; // multiple default assignments
    
    circle_t c = '{int: 0, radius: 1.0, int: 0};         // multiple *type*-default assignments
endmodule

module goodcode;
    int a[3:0] = '{0: 2, default: 3};
    
    typedef struct {
        int x;
        int y;
        real radius;
    } circle_t;
    
    circle_t b = '{radius: 1.0, default: 0};
    
    circle_t c = '{radius: 1.0, int: 0};
endmodule

Overwritten type key in assignment pattern

Sigasi Studio flags a warning for duplicate type member keys in assignment patterns (rule 30). This is not an error according to the language reference manual, but the last used type key overwrites previously matched members, making the code confusing and hard to maintain.

module uglycode;
    struct { int x, y; } a = '{int: 0, int: 1};
    int b[10] = '{int: 0, int: 1};
endmodule

module goodcode;
    struct { int x, y; } a = '{int: 1};
    int b[10] = '{int: 1};
endmodule

Duplicate member key in structure assignment pattern

Sigasi Studio flags an error for duplicate members/index keys in assignment patterns (rule 31). Each member/index key can occur only once.

module badcode;
	struct { int x, y; } a = '{x: 0, y: 0, x: 0};
	int b[10] = '{5: 1, 5: 2, default: 0};
endmodule

module goodcode;
	struct { int x, y; } a = '{x: 0, y: 0};
	int b[10] = '{5: 1, default:0};
endmodule

Mixed named and ordered notation in assignment pattern

Sigasi Studio flags an error when an assignment contains a mix of ordered and named elements (rule 32).

module badcode;
    // Mix of ordered and named associations: not correct
    struct { int x, y; } a = '{0, y: 1};
    int b[4] = '{0, 1, 2:5, 3:7};
endmodule
module ok_code;
    // Place binding: correct but may be harder to read, particularly with many elements
    struct { int x, y; } a = '{0, 1};
    int b[4] = '{0, 1, 5, 7};
endmodule
module goodcode;
    // Name binding: esay to understand and maintain
    struct { int x, y; } a = '{x: 0, y: 1};
    int b[4] = '{0: 0, 1: 1, 2: 5, 3: 7};
endmodule

Project specific setting of these rules

These rules can be disabled for your project, or its severity can be modified in the project linting settings.

Manual configuration in ${project location}/.settings/com.sigasi.hdt.verilog.linting.prefs:

28/severity/<project>=IGNORE

30/severity/<project>=IGNORE

31/severity/<project>=IGNORE

32/severity/<project>=IGNORE