Verilog keywords in VHDL

When choosing entity and port names in VHDL, it is recommended not to use (System)Verilog keywords. This will prevent problems if the VHDL entity ever has to be integrated in a mixed VHDL/Verilog project. Sigasi Studio will warn if a (System)Verilog keyword is used as an entity name.

entity always is port( -- always is a Verilog keyword: not recommended!

Project specific setting of this rule

This rule can be disabled for your project, or its severity can be modified in the project linting settings.

Manual configuration in ${project location}/.settings/com.sigasi.hdt.vhdl.linting.prefs:

192/severity/<project>=IGNORE