Vector width in assignments and port maps

Sigasi Studio checks the vector size in assignments and port maps. This check works at type-time and takes the (symbolic) value of generics into account.

Sigasi Studio will not take into account the value assigned to a generic in instantiations. The reasoning behind this is explained here.

Project specific setting of this rule

This rule can be disabled for your project, or its severity can be modified in the project linting settings.

Manual configuration in ${project location}/.settings/com.sigasi.hdt.vhdl.linting.prefs: