VHDL requires a sensitivity list for each process (or wait statements in the process body).
Sigasi Studio can warn about problems with your sensitivity list:
Presence of either a sensitivity list or one or more wait statements in a process (rule 38)
Incomplete sensitivity list (rule 72) (there is Quick Fix for this)
process(a ) begin c <= a and b; end process;
- Superfluous signals in sensitivity list (rule 73)
process(a, b, c) begin c <= a and b; end process;
- Duplicate signals in sensitivity list (rule 85)
process(a, b, b) begin c <= a and b; end process;
A sensitivity list should contain all signals that are read asynchronously in the process. For a combinatorial process, all signals read by the process should be in the sensitivity list. For a synchronous or clocked process, only the clock signal and an asynchronous reset signal (if present) should be in the sensitivity list. If that is not the case, your simulation results may be different from your synthesis results. Most synthesis tools ignore the sensitivity list. In traditional workflows, only the synthesis warnings will give you a hint that your sensitivity list is incomplete. This report will be available only hours or even days after you have finished typing your code. Flagging this problem earlier saves time and lets you catch the problem early.
Since VHDL-2008, you can write
process (all) to make sure you have
all necessary signals in the sensitivity list.
process(a, b) begin c <= a and b; end process;
process(clk) begin if rising_edge(clk) then -- code end if; end process;
process(clk, rst) begin if rst = '1' then -- reset code elsif rising_edge(clk) then -- code end if; end process;
process(all) begin c <= a and b; end process;
These rules can be disabled for your project, or its severity can be modified in the project linting settings.
Manual configuration in