Most VHDL designers prefer named associations in port and generic maps in instantiations. This makes it a lot easier to spot wrong connections. By default, Sigasi Studio warns when positional associations are used. You can change the severity of this check via Preferences > Sigasi > VHDL > Errors/Warnings in the Instantiation statement validation section.
architecture RTL of dut is component my_comp port ( clk : in std_logic; rst : in std_logic; inp : in std_logic; outp : out std_logic); end component; begin i_comp_1: my_comp port map( -- positional associations not recommended clk, rst, data_in(0), open ); i_comp_2: my_comp port map( -- named associations recommended clk => clk, rst => rst, inp => data_in(0), outp => open ); end architecture RTL;
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template: