Order of associations


Sigasi Studio gives a warning when the order of generics or ports in a map differs from the original generics or ports declaration order.

architecture RTL of dut is

   component my_comp port (
      clk: in std_logic;
      rst: in std_logic;
      inp: in std_logic;
      outp: out std_logic);
   end component;

begin
   assert iterations <= MAX_COUNT;

   i_comp_1: my_comp port map( -- associations should be kept in the same order as the declaration
      rst  => rst,
      clk  => clk,
      inp  => data_in(0), 
      outp => open
   );

   i_comp_1: my_comp port map(
      clk  => clk, 
      rst  => rst,
      inp  => data_in(0), 
      outp => open
   );

Project specific setting of this rule

This rule can be disabled for your project, or its severity can be modified in the project linting settings.

Manual configuration in ${project location}/.settings/com.sigasi.hdt.vhdl.linting.prefs:

177/severity/<project>=IGNORE