In VHDL, you can use ranges with
downto. But, if you use the
wrong direction, you get an empty range, which is usually not what you
signal foo: std_logic_vector(7 downto 0) -- range of 8; signal foo: std_logic_vector(7 to 0) -- null range;
We have a lint check that warns about this, even if you use constants or some simple arithmetic.
These rules can be disabled for your project, or its severity can be modified in the project linting settings.
Manual configuration in