On the Naming Conventions preference page (Window > Preferences > Sigasi > VHDL|Verilog/SystemVerilog > Naming Conventions) you can configure patterns to check correct naming of your VHDL and SystemVerilog identifiers. Patterns are configured with regex syntax.
The above defines the Naming Conventions for the entire workspace. To specify Naming Conventions for a project instead of for the entire workspace, have a look at Naming Conventions per project.
Only names with a specified pattern are checked. Empty patterns are omitted.
Example: to enforce a style where all variables have a
you would specify
.*_v pattern in the Variable name field.
This rule can be disabled for your project, or its severity can be modified in the project linting settings.
Manual configuration in