Naming Conventions

On the Naming Conventions preference page (Window > Preferences > Sigasi > VHDL|Verilog/SystemVerilog > Naming Conventions) you can configure patterns to check the correct naming of your VHDL, Verilog, and SystemVerilog identifiers. Two patterns can be set for an identifier: a valid pattern that the name of the identifier should match, and an invalid pattern that the name shouldn’t match. An identifier has to fulfill both conditions, so a name that matches both patterns is not valid. Patterns are configured using regex syntax .

Note: The Naming Conventions preference page is not yet available in the project preferences. If you require project-based configuration of the naming conventions rather than workspace preferences, please refer to the manual Rule configuration detailed below.

Only names with a specified pattern are checked. Empty patterns are omitted.

Example: to enforce a style where all variables have a _v suffix, and don’t contain numbers, you would specify .*_v for the valid pattern and .*[0-9].* for the invalid pattern in the Variable name field.

Rule configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured with the following template:

# Note: two patterns can be specified. These patterns are separated by a tab
# character. The first pattern specifies a *valid* pattern (something that must
# match), and the second pattern specifies an *invalid* pattern (something that
# can not match). If only a valid pattern is required, the tab character can
# be left out. If only an invalid pattern is required, the pattern should be
# specified after a (backslash-escaped) tab character.

# In the VHDL linting preferences file
92/params/alias_name/${path}=${regex}	${regex}
92/params/architecture_name/${path}=${regex}	${regex}
92/params/comment_header/${path}=${regex}	${regex}
92/params/concurrent_assignment_name/${path}=${regex}	${regex}
92/params/configuration_name/${path}=${regex}	${regex}
92/params/constant_name/${path}=${regex}	${regex}
92/params/context_declaration/${path}=${regex}	${regex}
92/params/entity_name/${path}=${regex}	${regex}
92/params/enumeration_literal_name/${path}=${regex}	${regex}
92/params/file_name/${path}=${regex}	${regex}
92/params/fsm_enumeration_literal_name/${path}=${regex}	${regex}
92/params/fsm_state_name/${path}=${regex}	${regex}
92/params/function_name/${path}=${regex}	${regex}
92/params/generate_statement_name/${path}=${regex}	${regex}
92/params/generic_name/${path}=${regex}	${regex}
92/params/instantiation_statement_name/${path}=${regex}	${regex}
92/params/label/${path}=${regex}	${regex}
92/params/package_name/${path}=${regex}	${regex}
92/params/procedure_name/${path}=${regex}	${regex}
92/params/port_name/${path}=${regex}	${regex}
92/params/input_port_name/${path}=${regex}	${regex}
92/params/output_port_name/${path}=${regex}	${regex}
92/params/inout_port_name/${path}=${regex}	${regex}
92/params/process_statement_name/${path}=${regex}	${regex}
92/params/signal_name/${path}=${regex}	${regex}
92/params/type_name/${path}=${regex}	${regex}
92/params/variable_name/${path}=${regex}	${regex}

# In the Verilog linting preferences file
2/params/class_name/${path}=${regex}	${regex}
2/params/comment_header/${path}=${regex}	${regex}
2/params/instantiation/${path}=${regex}	${regex}
2/params/interface_class_name/${path}=${regex}	${regex}
2/params/interface_name/${path}=${regex}	${regex}
2/params/module_name/${path}=${regex}	${regex}
2/params/package_name/${path}=${regex}	${regex}
2/params/program_name/${path}=${regex}	${regex}
2/params/subprogram_name/${path}=${regex}	${regex}
2/params/port_name/${path}=${regex}	${regex}
2/params/input_name/${path}=${regex}	${regex}
2/params/output_name/${path}=${regex}	${regex}
2/params/inout_name/${path}=${regex}	${regex}
2/params/parameter_name/${path}=${regex}	${regex}
2/params/net_name/${path}=${regex}	${regex}
2/params/var_name/${path}=${regex}	${regex}
2/params/ud_nettype_name/${path}=${regex}	${regex}
2/params/typedef_name/${path}=${regex}	${regex}
2/params/enum_typedef_name/${path}=${regex}	${regex}
2/params/enum_member_name/${path}=${regex}	${regex}
2/params/generate_block_name/${path}=${regex}	${regex}


A manual VHDL configuration where all ports must start with p_ except inout ports which must start with b_, and where input ports cannot contain numbers. We mark the ports with error markers if they don’t comply.

92/params/input_port_name=\	.*[0-9].*