Incorrect Vector Range Direction

VHDL allows arrays with both ascending (to) and descending ranges (downto). For vectors (one-dimensional arrays of scalars, e.g. bit or (u)logic) using a descending range is recommended. In this case leftmost bit is the MSB and the rightmost bit is the LSB, and that is what is assumed by the VHDL standard library’s arithmetic operators. Using an ascending range for vectors is also possible, however, it’s recommended to use a consistent style.

entity Downto_vectors is
       G0_g    : bit_vector(0 to 7);
       G1_g    : bit_vector(7 downto 0);
end entity Downto_vectors;

This rule can be configured by setting the desired vector range direction, either ascending or descending.

Note that this rule is set to ignore ignore by default.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template: