Sigasi Studio can check that each choice is specified only once in case and case generate statements as well as selected signal and variable assignments.
process is
variable state : std_logic_vector(2 downto 0) := "000";
constant IDLE : std_logic_vector := "110";
begin
case state is
when "000" => state := IDLE;
when "110" => state := "000";
when IDLE => state := "100";
end case;
end process;
Rule configuration
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:
14/severity/${path}={error|warning|info|ignore}